2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献_第6页

Reconciling QoS and Concurrency in NVIDIA GPUs via Warp-Level Scheduling 通过Warp-Level调度协调NVIDIA gpu的QoS和并发性

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774761

Jayati Singh, Ignacio Sañudo Olmedo, Nicola Capodieci, A. Marongiu, M. Caccamo

{"title":"Reconciling QoS and Concurrency in NVIDIA GPUs via Warp-Level Scheduling","authors":"Jayati Singh, Ignacio Sañudo Olmedo, Nicola Capodieci, A. Marongiu, M. Caccamo","doi":"10.23919/DATE54114.2022.9774761","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774761","url":null,"abstract":"The widespread deployment of NVIDIA GPUs in latency-sensitive systems today requires predictable GPU multi-tasking, which cannot be trivially achieved. The NVIDIA CUDA API allows programmers to easily exploit the processing power provided by these massively parallel accelerators and is one of the major reasons behind their ubiquity. However, NVIDIA GPUs and the CUDA programming model favor throughput instead of latency and timing predictability. Hence, providing real-time and quality-of-service (QoS) properties to GPU applications presents an interesting research challenge. Such a challenge is paramount when considering simultaneous multikernel (SMK) scenarios, wherein kernels are executed concurrently within each streaming multiprocessor (SM). In this work, we explore QoS-based fine-grained multitasking in SMK via job arbitration at the lowest level of the GPU scheduling hierarchy, i.e., between warps. We present QoS-aware warp scheduling (QAWS) and evaluate it against state-of-the-art, kernel-agnostic policies seen in NVIDIA hardware today. Since the NVIDIA ecosystem lacks a mechanism to specify and enforce kernel priority at the warp granularity, we implement and evaluate our proposed warp scheduling policy on GPGPU-Sim. QAWS not only improves the response time of the higher priority tasks but also has comparable or better throughput than the state-of-the-art policies.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128844354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Remote Sensing with UAV and Mobile Recharging Vehicle Rendezvous 无人机遥感与机动充电车交会

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774645

M. Ostertag, Jason Ma, T. Simunic

引用次数: 0

Non-Volatile Phase Change Material based Nanophotonic Interconnect 基于非挥发性相变材料的纳米光子互连

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774648

Parya Zolfaghari, Joel Ortiz, C. Killian, S. L. Beux

引用次数: 1

Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions 先进半导体解决方案的物理和功能逆向工程挑战

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774610

Bernhard Lippmann, A. Bette, Matthias Ludwig, Johannes Mutter, Johanna Baehr, Alexander Hepp, H. Gieser, Nicola Kovač, Tobias Zweifel, M. Rasche, Oliver Kellermann

引用次数: 4

Adding Dual Variables to Algebraic Reasoning for Gate-Level Multiplier Verification 门级乘法器验证的代数推理中加入对偶变量

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774587

Daniela Kaufmann, P. Beame, Armin Biere, J. Nordström

引用次数: 5

A Flash-based Current-mode IC to Realize Quantized Neural Networks 基于flash的电流模式集成电路实现量化神经网络

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774539

Kyler R. Scott, Cheng-Yen Lee, S. Khatri, S. Vrudhula

{"title":"A Flash-based Current-mode IC to Realize Quantized Neural Networks","authors":"Kyler R. Scott, Cheng-Yen Lee, S. Khatri, S. Vrudhula","doi":"10.23919/DATE54114.2022.9774539","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774539","url":null,"abstract":"This paper presents a mixed-signal architecture for implementing Quantized Neural Networks (QNNs) using flash transistors to achieve extremely high throughput with extremely low power, energy and memory requirements. Its low resource consumption makes our design especially suited for use in edge devices. The network weights are stored in-memory using flash transistors, and nodes perform operations in the analog current domain. Our design can be programmed with any QNN whose hyperparameters (the number of layers, filters, or filter size, etc) do not exceed the maximum provisioned. Once the flash devices are programmed with a trained model and the IC is given an input, our architecture performs inference with zero access to off-chip memory. We demonstrate the robustness of our design under current-mode non-linearities arising from process and voltage variations. We test validation accuracy on the ImageNet dataset, and show that our IC suffers only 0.6% and 1.0% reduction in classification accuracy for Top-1 and Top-5 outputs, respectively. Our implementation results in a $sim boldsymbol {50}times$ reduction in latency and energy when compared to a recently published mixed-signal ASIC implementation, with similar power characteristics. Our approach provides layer partitioning and node sharing possibilities, which allow us to trade off latency, power, and area amongst each other.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126524387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Practical identity recognition using WiFi's Channel State Information 使用WiFi的信道状态信息进行身份识别

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774772

Cristian Turetta, Florenc Demrozi, Philipp H. Kindt, Alejandro Masrur, G. Pravadelli

{"title":"Practical identity recognition using WiFi's Channel State Information","authors":"Cristian Turetta, Florenc Demrozi, Philipp H. Kindt, Alejandro Masrur, G. Pravadelli","doi":"10.23919/DATE54114.2022.9774772","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774772","url":null,"abstract":"Identity recognition is increasingly used to control access to sensitive data, restricted areas in industrial, healthcare, and defense settings, as well as in consumer electronics. To this end, existing approaches are typically based on collecting and analyzing biometric data and imply severe privacy con-cerns. Particularly when cameras are involved, users might even reject or dismiss an identity recognition system. Furthermore, iris or fingerprint scanners, cameras, microphones, etc., imply installation and maintenance costs and require the user's active participation in the recognition procedure. This paper proposes a non-intrusive identity recognition system based on analyzing WiFi's Channel State Information (CSI). We show that CSI data attenuated by a person's body and typical movements allows for a reliable identification - even in a sitting posture. We further propose a lightweight deep learning algorithm trained using CSI data, which we implemented and evaluated on an embedded platform (i.e., a Raspberry Pi 4B). Our results obtained using real-world experiments suggest a high accuracy in recognizing people's identity, with a specificity of 98% and a sensitivity of 99%, while requiring a low training effort and negligible cost.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124424361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Discrete Samplers for Approximate Inference in Probabilistic Machine Learning 概率机器学习中近似推理的离散采样器

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774623

Shirui Zhao, Nimish Shah, Wannes Meert, M. Verhelst

{"title":"Discrete Samplers for Approximate Inference in Probabilistic Machine Learning","authors":"Shirui Zhao, Nimish Shah, Wannes Meert, M. Verhelst","doi":"10.23919/DATE54114.2022.9774623","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774623","url":null,"abstract":"Probabilistic reasoning models (PMs) and probabilistic inference bring advantages when dealing with small datasets or uncertainty on the observed data, and allow to integrate expert knowledge and create interpretable models. The main challenge of using these PMs in practice is that their inference is very compute-intensive. Therefore, custom hardware architectures for the exact and approximate inference of PMs have been proposed in the SotA. The throughput, energy and area efficiency of approximate PM inference accelerators are strongly dominated by the sampler blocks required to sample arbitrary discrete distributions. This paper proposes and studies novel discrete sampler architectures towards efficient and flexible hardware implementations for PM accelerators. Both cumulative distribution table (CDT) and Knuth-Yao (KY) based sampling algorithms are assessed, based on which different sampler hardware architectures were implemented. Innovation is brought in terms of a reconfigurable CDT sampling architecture with a flexible range and a reconfigurable Knuth-Yao sampling architecture that supports both flexible range and dynamic precision. All architectures are benchmarked on real-world Bayesian Networks, demonstrating up to 13 × energy efficiency benefits and 11 × area efficiency improvement of the optimized reconfigurable Knuth-Yao sampler over the traditional linear CDT-based samplers used in the PM SotA.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127452615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Space and Power Reduction in BDD-based Optical Logic Circuits Exploiting Dual Ports 利用双端口的基于bdd的光逻辑电路的空间和功耗降低

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774637

R. Matsuo, S. Minato

{"title":"Space and Power Reduction in BDD-based Optical Logic Circuits Exploiting Dual Ports","authors":"R. Matsuo, S. Minato","doi":"10.23919/DATE54114.2022.9774637","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774637","url":null,"abstract":"Optical logic circuits based on integrated nanophotonics have attracted significant interest due to their ultra-high-speed operation. A synthesis method based on the Binary Decision Diagram (BDD) has been studied, as BDD-based optical logic circuits can take advantage of the speed of light. However, a fundamental disadvantage of BDD-based optical logic circuits is a large number of splitters, which results in large power consumption. In BDD-based circuits a dual port of each logic gate is not used. We propose a method for eliminating a splitter exploiting this dual port. We define a BDD node corresponding to a dual port as a dual port node (DP node) and call the proposed method DP node sharing. We demonstrated that DP node sharing significantly reduces the power consumption and to a lesser extent circuit size without increasing delay. We conducted an experiment involving 10-input logic functions obtained by applying an LUT technology mapper to an ISCSA'85 C7552 benchmark circuit to evaluate our DP node sharing. The experimental results demonstrated that DP node sharing reduces the power consumption by two orders of magnitude of circuit that consume a large amount of power.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130378053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Towards Approximate Computing for Achieving Energy vs. Accuracy Trade-offs 实现能量与精度权衡的近似计算

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774538

A. Ometov, J. Nurmi

引用次数: 6