2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献

SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions SNE:稀疏事件卷积的能量比例数字加速器

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.48550/arXiv.2204.10687

Alfio Di Mauro, A. S. Prasad, Zhikai Huang, Matteo Spallanzani, Francesco Conti, L. Benini

引用次数: 12

Flodam: Cross-Layer Reliability Analysis Flow for Complex Hardware Designs 复杂硬件设计的跨层可靠性分析流程

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774541

A. Kritikakou, O. Sentieys, G. Hubert, Youri Helen, Jean-Francois Coulon, P. Deroux-Dauphin

引用次数: 1

Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach 探索可重构纳米技术的标准电池设计:一种正式方法

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774620

Michael Raitza, Steffen Märcker, Shubham Rai, Akash Kumar

引用次数: 1

MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping 深度神经网络硬件映射的多目标进化方法

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774747

Enrico Russo, M. Palesi, Salvatore Monteleone, Davide Patti, G. Ascia, V. Catania

{"title":"MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware Mapping","authors":"Enrico Russo, M. Palesi, Salvatore Monteleone, Davide Patti, G. Ascia, V. Catania","doi":"10.23919/DATE54114.2022.9774747","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774747","url":null,"abstract":"Deep Neural Networks (DNNs) embedded domain-specific accelerators enable inference on resource-constrained devices. Making optimal design choices and efficiently scheduling neural network algorithms on these specialized architectures is challenging. Many choices can be made to schedule computation spatially and temporally on the accelerator. Each choice influences the access pattern to the buffers of the architectural hierarchy, affecting the energy and latency of the inference. Each mapping also requires specific buffer capacities and a number of spatial components instances that translate in different chip area occupation. The space of possible combinations, the mapping space, is so large that automatic tools are needed for its rapid ex-ploration and simulation. This work presents MEDEA, an open-source multi-objective evolutionary algorithm based approach to DNNs accelerator mapping space exploration. MEDEA leverages the Timeloop analytical cost model. Differently from the other schedulers that optimize towards a single objective, MEDEA allows deriving the Pareto set of mappings to optimize towards multiple, sometimes conflicting, objectives simultaneously. We found that solutions found by MEDEA dominates in most cases those found by state-of-the-art mappers.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128428093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Self-Terminating Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing 高效神经形态计算的多级Cell ReRAM自终止写入

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774550

Zongwu Wang, Zhezhi He, Rui Yang, Shiquan Fan, Jie Lin, Fangxin Liu, Yueyang Jia, Chenxi Yuan, Qidong Tang, Li Jiang

{"title":"Self-Terminating Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing","authors":"Zongwu Wang, Zhezhi He, Rui Yang, Shiquan Fan, Jie Lin, Fangxin Liu, Yueyang Jia, Chenxi Yuan, Qidong Tang, Li Jiang","doi":"10.23919/DATE54114.2022.9774550","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774550","url":null,"abstract":"The Resistive Random-Access-Memory (ReRAM) in crossbar structure has shown great potential in accelerating the vector-matrix multiplication, owing to the fascinating computing complexity reduction (from O(n2) to O(1)). Nevertheless, the ReRAM cells still encounter device programming variation and resistance drifting during computation (known as read disturbance), which significantly hamper its analog computing precision. Inspired by prior precise memory programming works, we propose a Self-Terminating Write (STW) circuit for Multi-Level Cell (MLC) ReRAM. In order to minimize the area overhead, the design heavily reuses inherent computing peripherals (e.g., Analog-to-Digital Converter and Trans-Impedance Amplifier) in conventional dot-product engine. Thanks to the fast and precise programming capability of our design, the ReRAM cell can possess 4 linear distributed conductance levels, with minimum latency used for intermediate resistance refreshing. Our comprehensive cross-layer (device/circuit/architecture) simulation indicates that the proposed MLC STW scheme can effectively obtain 2-bit precision via a single programming pulse. Besides, our design outperforms the prior write&verify schemes by 4.7× and 2× in programming latency and energy, respectively.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129146988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

DWR: Differential Wearing for Read Performance Optimization on High-Density NAND Flash Memory 基于差分磨损的高密度NAND快闪记忆体读取性能优化

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774738

Yunpeng Song, Qiao Li, Yina Lv, Changlong Li, Liang Shi

引用次数: 2

ENCORE Compression: Exploiting Narrow-width Values for Quantized Deep Neural Networks ENCORE压缩:利用量化深度神经网络的窄宽度值

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774545

Myeongjae Jang, Jinkwon Kim, Jesung Kim, Soontae Kim

{"title":"ENCORE Compression: Exploiting Narrow-width Values for Quantized Deep Neural Networks","authors":"Myeongjae Jang, Jinkwon Kim, Jesung Kim, Soontae Kim","doi":"10.23919/DATE54114.2022.9774545","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774545","url":null,"abstract":"Deep Neural Networks (DNNs) become a practical machine learning algorithm running on various Neural Processing Units (NPUs). For higher performance and lower hardware overheads, DNN datatype reduction through quantization is proposed. Moreover, to solve the memory bottleneck caused by large data size in DNNs, several zero value-aware compression algorithms are used. However, these compression algorithms do not compress modern quantized DNNs well because of decreased zero values. We find that the latest quantized DNNs have data redundancy due to frequent narrow-width values. Because low-precision quantization reduces DNN datatypes to a simple datatype with less bits, scattered DNN data are gathered to a small number of discrete values and incur a biased data distribution. Narrow-width values occupy a large proportion of the biased distribution. Moreover, an appropriate zero run-length bits can be dynamically changed according to DNN sparsity. Based on this observation, we propose a compression algorithm that exploits narrow-width values and variable zero run-length for quantized DNNs. In experiments with three quantized DNNs, our proposed scheme yields an average compression ratio of 2.99.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129453373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Using ontologies for dataset engineering in automotive AI applications 在汽车人工智能应用中使用本体进行数据集工程

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774675

Martin Herrmann, Christian Witt, Laureen Lake, Stefani Guneshka, Christian Heinzemann, Frank Bonarens, P. Feifel, Simon Funke

引用次数: 9

Salvaging Runtime Bad Blocks by Skipping Bad Pages for Improving SSD Performance 通过跳过坏页来挽救运行时坏块以提高SSD性能

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774677

Junoh Moon, Mincheol Kang, Wonyoung Lee, Soontae Kim

引用次数: 2

Energy-Efficient Brain-Inspired Hyperdimensional Computing Using Voltage Scaling 使用电压缩放的高能效大脑启发的超维计算

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2022-03-14 DOI: 10.23919/DATE54114.2022.9774697

Sizhe Zhang, Ruixuan Wang, Dongning Ma, J. Zhang, Xunzhao Yin, Xun Jiao

{"title":"Energy-Efficient Brain-Inspired Hyperdimensional Computing Using Voltage Scaling","authors":"Sizhe Zhang, Ruixuan Wang, Dongning Ma, J. Zhang, Xunzhao Yin, Xun Jiao","doi":"10.23919/DATE54114.2022.9774697","DOIUrl":"https://doi.org/10.23919/DATE54114.2022.9774697","url":null,"abstract":"Recently, brain-inspired hyperdimensional computing (HDC) has demonstrated promising capability in a wide range of applications such as medical diagnosis, human activity recognition, and voice classification, etc. Despite the growing popularity of HDC, its memory-centric computing characteristics make the associative memory implementation under significant energy consumption due to the massive data storage and processing. In this paper, we present a systematic case study to leverage the application-level error resilience of HDC to reduce the energy consumption of HDC associative memory by using voltage scaling. Evaluation results on various applications show that our proposed approach can achieve 47.6% energy saving on associative memory with a 1% accuracy loss. We further explore two low-cost error masking methods: word masking and bit masking, to mitigate the impact of voltage scaling-induced errors. Experimental results show that the proposed word masking (bit masking) method can further enhance energy saving up to 62.3% (72.5%) with accuracy loss ≤1%.","PeriodicalId":232583,"journal":{"name":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126018334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8