2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)最新文献_第3页

Tunnel FETs with tunneling normal to the gate 隧穿法向栅极的隧道场效应管

2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S) Pub Date : 2013-10-01 DOI: 10.1109/E3S.2013.6705871

H. Xing, Guangle Zhou, Mingda Li, Yiqing Lu, Rui Li, M. Wistey, P. Fay, D. Jena, A. Seabaugh

引用次数: 2

Sub-Boltzmann transistors with piezoelectric gate barriers 压电栅极阻挡的亚玻尔兹曼晶体管

2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S) Pub Date : 2013-10-01 DOI: 10.1109/E3S.2013.6705877

R. Jana, G. Snider, D. Jena

引用次数: 3

Efficient optical interconnections for data-center computing systems 数据中心计算系统的高效光互连

2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S) Pub Date : 2013-10-01 DOI: 10.1109/E3S.2013.6705884

A. Krishnamoorthy

{"title":"Efficient optical interconnections for data-center computing systems","authors":"A. Krishnamoorthy","doi":"10.1109/E3S.2013.6705884","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705884","url":null,"abstract":"Within the past decade, the semiconductor computing industry has developed multicore and multithreaded core processors to overcome the challenges and shrinking benefits of traditional technology scaling. Multichip systems built using these components will require immense amount of off-chip bandwidth and low latency chip-to-chip links at the lowest energy cost possible. Wavelength-division multiplexed (WDM) silicon photonics have the potential to provide a solution for this immense interconnect problem. At Oracle, we are aggressively building a portfolio of active and passive nanophotonic devices, circuits, and multichip packaging with the aim to achieve sub-picojoule per bit communication links between computing elements in a large array “Macrochip”. To achieve ultralow energy consumption will certainly require integrating best-in-breed photonic devices with electronic circuits. While the juxtaposition of silicon photonic devices and VLSI circuits on the same silicon substrate represents the most intimate integration of electronic and photonic technologies, achieving this will require an immense amount of sophistication in design and process integration. Instead, hybrid integration of aggressive components, built on individually optimized technology platforms, is a pragmatic approach to achieving peak performance. Such “photonic bridge” chip components may be used as units in a larger transmitter or receiver array or as drop-in communication physical layer elements in a multi-chip computing node.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134601936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Prospects for high-aspect-ratio FinFETs in low-power logic 低功耗逻辑中高宽高比finfet的前景

2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S) Pub Date : 2013-10-01 DOI: 10.1109/E3S.2013.6705878

M. Rodwell, D. Elias

{"title":"Prospects for high-aspect-ratio FinFETs in low-power logic","authors":"M. Rodwell, D. Elias","doi":"10.1109/E3S.2013.6705878","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705878","url":null,"abstract":"As we reduce transistor capacitances, node capacitances are limited by wiring, setting a minimum power dissipation determined by the number of gates, the mean wire length, the mean switching rate, and the supply voltage VDD. With thermally-activated, FETs, the off-state leakage Ioff and target on-current Ion then determine the minimum feasible VDD, and the IC clock frequency can then be increased only at the expense of increased power consumption. Tunnel transistors [1] offer subthreshold characteristics steeper than 60mV/decade, but achieving high Ion at low Ioff and low VDD is challenging. Subthreshold logic [2] operates at lowVDD, but is slow because of low Ion. Here we propose low-power logic using high-aspect-ratio finFETs, devices we have fabricated with few-nm body thicknesses and 180nm height [3]. If these can fabricated at ~20nm pitch, then the fin surface area can exceed its footprint area - i.e. the area the transistor occupies on the IC - by ~10:1. IC performance can be then improved by maintaining fixed VDD, but with reduced FET footprint area hence reduced die size and therefore reduced wiring capacitance, or can be improved by reducing VDD to ~300mV while maintaining large Ion per unit IC die area.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116680922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

2.5 GB/s germanium gate photoMOSFET integrated to silicon photonics 集成到硅光子学的2.5 GB/s锗栅photoMOSFET

2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S) Pub Date : 2013-10-01 DOI: 10.1109/E3S.2013.6705885

R. Going, Jodi Loo, Tsu-Jae King-Liu, Ming C. Wu

引用次数: 0

Why tunneling FETs don't work, and how to fix it 为什么隧道效应晶体管不工作，如何解决它

2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S) Pub Date : 2013-10-01 DOI: 10.1109/E3S.2013.6705868

S. Agarwal, E. Yablonovitch

{"title":"Why tunneling FETs don't work, and how to fix it","authors":"S. Agarwal, E. Yablonovitch","doi":"10.1109/E3S.2013.6705868","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705868","url":null,"abstract":"To date, TFET results have been unsatisfying. The best reported subthreshold swings have been measured at a current density of around a nA/um and get significantly worse as the current increases. In order to achieve a better performance, there are fundamental design issues that need to be engineered. We can understand these issues by analyzing the three types of devices shown in Fig 1. The voltage required to operate a TFET can be given by: VDD = VSS × Log(Ion /Ioff)+ VOV. VSS is the subthreshold swing and VOV is the overdrive voltage needed to achieve the desired on-current after threshold. VOV will be determined by the device geometry as shown in Fig 2 [1]. Introducing quantum confinement in the direction of tunneling increases the conductance by 1-2 orders of magnitude at low voltage. VSS is given by the following model [2]: SS = 1/ ηel × (1/SBarrier + ηconf/SDOS)-1 (1) ηel is the electrostatic gate efficiency. ηconf is the quantum confinement efficiency and comes from energy level shifts that occur when the quantum well shape changes with bias. SBarrier represents the steepness in mV/decade that comes from changing the thickness of the tunneling barrier. SDOS is the steepness of the joint density of states (DOS) and represents the rate at which the joint DOS fall off as the band edges are misaligned.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134080595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Exascale computer architecture adjusting to the “New normal” for computing 百亿亿级计算机架构适应计算的“新常态”

2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S) Pub Date : 2013-10-01 DOI: 10.1109/E3S.2013.6705854

J. Shalf

{"title":"Exascale computer architecture adjusting to the “New normal” for computing","authors":"J. Shalf","doi":"10.1109/E3S.2013.6705854","DOIUrl":"https://doi.org/10.1109/E3S.2013.6705854","url":null,"abstract":"The current MPI+Fortran ecosystem has sustained HPC application software development for the past decade, but was architected for coarse-grained concurrency largely dominated by bulk-synchronous algorithms. The trends in computer architecture have turned our model for how to get good performance from computing systems upside-down, and will require rethinking our entire programming environment and algorithm design to be better aligned with the new cost metrics for these emerging hardware architectures. There are already promising avenues of exploration underway to mitigate these effects. Future hardware constraints on bandwidth and memory capacity, together with exponential growth in explicit on-chip parallelism will likely require a mass migration to new algorithms and software architecture that is as broad and disruptive as the migration from vector to parallel computing systems that occurred 15 years go. The challenge is to efficiently express massive parallelism and hierarchical data locality without subjecting the programmer to overwhelming complexity. The author covers how changes in hardware (governed by the fundamental physics of Silicon based CMOS technology) are breaking our existing abstract machine models, and DOE's program to overcome these obstacles to continued performance improvements. He examines potential approaches that range from revolutionary asynchronous and dataflow models of computation to evolutionary extensions to existing APIs and OpenMP directives.","PeriodicalId":231837,"journal":{"name":"2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130084026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Waveguide-integrated optical antenna nanoLEDs for on-chip communication 用于片上通信的波导集成光学天线纳米oled

2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S) Pub Date : 2013-10-01 DOI: 10.1109/E3S.2013.6705886

M. Eggleston, K. Messer, S. Fortuna, E. Yablonovitch, Ming C. Wu

引用次数: 0

Nanoelectromechanical switching devices: Scaling toward ultimate energy efficiency and longevity 纳米机电开关器件:向终极能源效率和寿命扩展

2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S) Pub Date : 2013-10-01 DOI: 10.1109/E3S.2013.6705881

P. Feng

引用次数: 0

Achieving energy efficiency by HW/SW co-design 通过硬件/软件协同设计实现能源效率

2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S) Pub Date : 2013-10-01 DOI: 10.1109/E3S.2013.6705856

S. Borkar

引用次数: 5