2013 International Symposium on System on Chip (SoC)最新文献

Study of adaptive detection for MIMO-OFDM systems MIMO-OFDM系统的自适应检测研究

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675276

Essi Suikkanen, Janne Janhunen, S. Shahabuddin, M. Juntti

{"title":"Study of adaptive detection for MIMO-OFDM systems","authors":"Essi Suikkanen, Janne Janhunen, S. Shahabuddin, M. Juntti","doi":"10.1109/ISSoC.2013.6675276","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675276","url":null,"abstract":"Requirements for higher data rates and lower power consumption set new challenges for implementation of multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) receivers. Simple detectors have the advantage of low complexity and power consumption, but they cannot offer as good performance as more complex detectors. Therefore it would be beneficial to be able to adapt the detector algorithm to suit the channel conditions to minimize the receiver processing power consumption while satisfying the quality of service requirements. At low signal-to-noise ratio (SNR) and/or low rank channel, more power and computation resources could be used for detection in order to guarantee reliable communication, while in good conditions, a simple and less power consuming detector could be used. In this paper, we compare the performance of different detection algorithms. The performance results are based on simulations in long term evolution (LTE) system. The effect of precoding and hybrid automatic repeat request (HARQ) on the performance is shown. Implementation results based on the existing literature are included in the comparison. We discuss when it would be beneficial to use a complex detector and when a simple one would be sufficient. Also the switching criterion is discussed.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121102377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Partitioning constraints and signal routing approach for multi-FPGA prototyping platform 多fpga原型平台的划分约束和信号路由方法

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675273

M. Turki, H. Mehrez, Z. Marrakchi, M. Abid

引用次数: 4

Framework for industrial embedded system product development and management 框架工业嵌入式系统产品开发和管理

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675265

Arttu Leppakoski, E. Salminen, T. Hämäläinen

引用次数: 5

Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms 优化并行多核平台中片上网络路由重新配置的开销

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675258

Marco Balboni, F. Triviño, J. Flich, D. Bertozzi

{"title":"Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms","authors":"Marco Balboni, F. Triviño, J. Flich, D. Bertozzi","doi":"10.1109/ISSoC.2013.6675258","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675258","url":null,"abstract":"In order to cope with an increased level of resource contention and dynamic application behaviour, the runtime reconfiguration of the routing function of an on-chip interconnection network is a desirable feature for multi-core hardware platforms in the embedded computing domain. The most intuitive approach consists of draining the network from ongoing packets before reconfiguring its routing tables, thus preventing the occurrence of deadlock from the ground up. The impact on application performance is however unacceptable. On the other hand, truly dynamic approaches are too much of an overhead for an on-chip setting. Recently, the overlapped static reconfiguration (OSR) method was proven to be capable of routing reconfiguration in the presence of background traffic with only a mild impact on the resource budget. This work finds that this method is still far from materializing its potentials in terms of reconfiguration performance (both impact on background traffic, which is still there to some extent, and duration of the reconfiguration transient). Therefore, it proposes a set of optimization methods for OSR spanning the trade-off between performance improvements and implementation cost. To the limit, fully transparent reconfiguration is delivered.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127113986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Achieving QoS in NoC-based MPSoCs through Dynamic Frequency Scaling 通过动态频率缩放实现基于noc的mpsoc的QoS

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675275

G. Guindani, F. Moraes

{"title":"Achieving QoS in NoC-based MPSoCs through Dynamic Frequency Scaling","authors":"G. Guindani, F. Moraes","doi":"10.1109/ISSoC.2013.6675275","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675275","url":null,"abstract":"The management of Quality-of-Service (QoS) constraints in NoC-based MPSoCs, with dozens of tasks running simultaneously, is still a challenge. Techniques applied at design or run-time to address this issue adopts different QoS metrics. Designers include in their systems monitoring techniques, adapting at run-time the QoS parameters to cope with the required constraints. In order words, MPSoC are able to self-adapt themselves, while executing a given set of applications. Self-adaptation capability is a key feature to meet applications' requirements in dynamic systems. Dynamic Voltage and Frequency Scaling (DVFS) is an adaptation technique frequently used to reduce the overall energy consumption, not coupled to QoS constraints, as throughput or latency. Another example of adaptation technique is task migration, which focus on throughput or latency optimization. The self-adaptation technique proposed in this paper adopts Dynamic Frequency Scaling (DFS) trading-off power consumption and QoS constraints. Each processor running the applications' tasks initially reaches a steady state leading each task to a frequency level that optimizes the communication with neighbor tasks. The goal of the initial state is to reach a trade-off between power consumption and communication throughput. Next, the application performance is monitored to adjust the frequency level of each task according to the QoS parameters. Results show that the proposed self-adaptability scheme can meet the required QoS constraints, by changing the frequency of the PEs running the application tasks.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131465100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

SW and HW speculative Nelder-Mead execution for high performance unconstrained optimization SW和HW推测Nelder-Mead执行高性能无约束优化

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675279

Artur Mariano, Paulo Garcia, T. Gomes

引用次数: 4

A cycle accurate simulation framework for asynchronous NoC design 异步NoC设计的周期精确仿真框架

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675263

F. Terraneo, Davide Zoni, W. Fornaciari

引用次数: 10

ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores ViSA:一个高效的插槽架构，支持多目标ASIP内核

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675270

P. Figuli, Carsten Tradowsky, Nadine Gaertner, J. Becker

{"title":"ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores","authors":"P. Figuli, Carsten Tradowsky, Nadine Gaertner, J. Becker","doi":"10.1109/ISSoC.2013.6675270","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675270","url":null,"abstract":"Field Programmable Gate Arrays (FPGA) are widely used to accelerate parallel applications by specialized hardware. Especially for data flow intensive applications FPGAs are very well suited to design application specific data paths with a certain degree of parallelism. Since most of applications also need control flow, the most common method is to design complex state machines that are realized in hardware. However, this often leads to very high and inefficient resource utilization on the target architecture for design parts that are not performance critical nor relevant for more efficient realizations. In this paper, we propose a generic VLIW-inspired Slot Architecture (ViSA), which combines two efficient objectives, the performance of parallel hardware and the low area utilization of custom processors. Furthermore, we introduce the methodology for mapping and debugging applications on the efficient ViSA architecture.We present experimental results of two corner case applications showing that our approach is suitable for ultra low power as well as high performance computing. Using the presented co-design methodology, we will conclude that ViSA enables the realization of multi-objective design spaces for various target domains. ViSA has extreme throughput at low operating frequencies leading to significant power and energy savings over state of the art architectures.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128597182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Adaptive QoS techniques for NoC-based MPSoCs 基于noc的mpsoc自适应QoS技术

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675274

Marcelo Ruaro, E. Carara, F. Moraes

{"title":"Adaptive QoS techniques for NoC-based MPSoCs","authors":"Marcelo Ruaro, E. Carara, F. Moraes","doi":"10.1109/ISSoC.2013.6675274","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675274","url":null,"abstract":"With the significant increase in the number of processing elements in NoC-Based MPSoCs, communication becomes, increasingly, a critical resource for performance gains and QoS guarantees. The main gap observed in the NoC-Based MPSoCs literature is the runtime adaptive techniques to meet QoS. In the absence of such techniques, the system user must statically define the resource distribution to each real-time task. The goal of this research is to investigate the runtime adaptation of the NoC resources, according to the QoS requirements of each application running in the MPSoC. The adaptive techniques presented in this work focused in adaptive routing, flow priorities, and switching mode. The monitoring and adaptation management is performed at the operating system level, ensuring QoS to the monitored applications. Monitoring and QoS adaptation were implemented in software. In the experiments, applications with latency and throughput deadlines run concurrently with best-effort applications. Results with real applications reduced in average 60% the number of latency violations, ensuring smaller jitter and higher throughput. The execution time of applications is not penalized applying the proposed QoS adaptation methods.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126592413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Efficient on-chip vector processing for multicore processors 有效的片上矢量处理多核处理器

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675260

S. F. Beldianu, Sotirios G. Ziavras

引用次数: 0