2013 International Symposium on System on Chip (SoC)最新文献_第2页

Evaluating the scalability of test buses 评估测试总线的可伸缩性

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675278

Alexandre M. Amory, Matheus T. Moreira, Ney Laert Vilar Calazans, F. Moraes, C. Lazzari, M. Lubaszewski

引用次数: 0

A novel SAD architecture for variable block size motion estimation in HEVC video coding 一种用于HEVC视频编码中可变块大小运动估计的SAD结构

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675269

Purnachand Nalluri, L. N. Alves, A. Navarro

引用次数: 37

Crosstalk avoidance coding for reliable data transmission of network on chips 芯片上网络可靠数据传输的串扰避免编码

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675266

Z. Shirmohammadi, S. Miremadi

引用次数: 16

On the impact of dynamic data management for distributed local memories in heterogeneous MPSoCs 动态数据管理对异构mpsoc中分布式本地存储器的影响

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675267

Benedikt Noethen, Oliver Arnold, G. Fettweis

引用次数: 0

Efficient distributed memory management in a multi-core H.264 decoder on FPGA 基于FPGA的多核H.264解码器的高效分布式内存管理

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675256

Jiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, A. Jantsch

引用次数: 2

Prefetching across a shared memory tree within a Network-on-Chip architecture 在片上网络体系结构中跨共享内存树进行预取

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675268

Jamie Garside, N. Audsley

引用次数: 19

Comparison of analog transactions using statistics 使用统计比较模拟事务

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675282

Alexander W. Rath, Volkan Esen, W. Ecker

引用次数: 2

Scheduling of parallelized synchronous dataflow actors 并行同步数据流参与者的调度

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675271

Zheng Zhou, K. Desnos, M. Pelcat, J. Nezan, W. Plishker, S. Bhattacharyya

{"title":"Scheduling of parallelized synchronous dataflow actors","authors":"Zheng Zhou, K. Desnos, M. Pelcat, J. Nezan, W. Plishker, S. Bhattacharyya","doi":"10.1109/ISSoC.2013.6675271","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675271","url":null,"abstract":"Parallelization of Digital Signal Processing (DSP) software is an important trend for MultiProcessor System-on-Chip (MPSoC) implementation. The performance of DSP systems composed of parallelized computations depends on the scheduling technique, which must in general allocate computation and communication resources for competing tasks, and ensure that data dependencies are satisfied. In this paper, we formulate a new type of parallel task scheduling problem called Parallel Actor Scheduling (PAS) for MPSoC mapping of DSP systems that are represented as Synchronous DataFlow (SDF) graphs. In contrast to traditional SDF-based scheduling techniques, which focus on exploiting graph level (inter-actor) parallelism, the PAS problem targets the integrated exploitation of both intra- and inter-actor parallelism for platforms in which individual actors can be parallelized across multiple processing units. We address a special case of the PAS problem in which all of the actors in the DSP application or subsystem being optimized can be parallelized. For this special case, we develop and experimentally evaluate a two-phase scheduling framework with two work flows - particle swarm optimization with a mixed integer programming formulation, and particle swarm optimization with a fast heuristic based on list scheduling. We demonstrate that our PAS-targeted scheduling framework provides a useful range of trade-offs between synthesis time requirements and the quality of the derived solutions.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126217715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

FPGA-accelerated color edge detection using a Geometric-Algebra-to-Verilog compiler 使用几何代数到verilog编译器的fpga加速颜色边缘检测

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675272

Florian Stock, A. Koch, D. Hildenbrand

引用次数: 12

System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems 系统互连扩展，在低成本的MMU-less嵌入式系统中实现完全透明的需求分页

2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675257

Lorenzo Zuolo, Gabriele Miorandi, C. Zambelli, P. Olivo, D. Bertozzi

{"title":"System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems","authors":"Lorenzo Zuolo, Gabriele Miorandi, C. Zambelli, P. Olivo, D. Bertozzi","doi":"10.1109/ISSoC.2013.6675257","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675257","url":null,"abstract":"MMU-less embedded systems are the state of the art solution for deeply embedded computing environments. Thanks to the rapid evolution of such devices, nowadays applications that run on top of them are evolving from simple control tasks to more complex applications that involve an Operating System (OS). At the same time, cost budget remains unchanged in spite of the growing performance requirements. For this reason, traditional code loading and execution techniques like full code shadowing or execute-in-place may lead to a performance bottleneck. Even demand paging strategies lack consensus due to the customization and the complexity of the software infrastructure dealing with the memory management. The objective of this work is to implement a transparent hardware-based demand paging strategy for code loading and execution, targeting MMU-less embedded systems. This approach consists of making the system interconnect aware of the memory map, without burdening on the legacy OS code, application code and on the compilation framework. This approach materializes lower boot-up latency and shorter application execution time with respect to traditional loading and executing schemes.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121940807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2