2013 International Symposium on System on Chip (SoC)最新文献

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A family of modular area- and energy-efficient QRD-accelerator architectures 一系列模块化面积和节能qrd加速器架构
2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675277
U. Vishnoi, T. Noll
{"title":"A family of modular area- and energy-efficient QRD-accelerator architectures","authors":"U. Vishnoi, T. Noll","doi":"10.1109/ISSoC.2013.6675277","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675277","url":null,"abstract":"QR-decomposition accelerators are attractive SoC components for many applications with a wide range of specifications. A new family of highly area- and energy-efficient, modular two-way linear-array QRD architectures based on the Givens algorithm and CORDIC rotations is proposed. The template architecture allows for implementations of real-/complex-valued and integer/floating-point QRDs. An accurate algebraic cost model enables cross-level optimization over architecture, micro-architecture and circuit level using a rich set of parameters. Quantitative results for exemplary applications are presented for implementations in 40-nm CMOS, proving the significant improvement of efficiency.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114101630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Split-cost communication model for improved MPSoC application mapping 改进MPSoC应用映射的分成本通信模型
2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675280
M. Odendahl, J. Castrillón, Vitaliy Volevach, R. Leupers, G. Ascheid
{"title":"Split-cost communication model for improved MPSoC application mapping","authors":"M. Odendahl, J. Castrillón, Vitaliy Volevach, R. Leupers, G. Ascheid","doi":"10.1109/ISSoC.2013.6675280","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675280","url":null,"abstract":"Automated mapping of dataflow applications to state-of-the-art, heterogeneous Multiprocessor Systems on Chip (MPSoCs) with complex interconnects and communication means is an ongoing research endeavor. We implement, measure and analyze three different communication libraries for a representative, off-the-shelf platform of this kind. The results of the analysis are used to show the need of a new cost model to properly characterize inter-task communication. Afterwards, this paper presents an algorithm to solve the mapping problem jointly for computation and communication using this cost model. A case study with four real streaming applications shows that the obtained mapping is able to reduce the execution time. Compared to a mapping decision where all channels are mapped to shared memory, the makespan fell down up to 10% due to an automated selection of a more appropriate communication library.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131611167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
TNODE: A low power sensor node processor for secure wireless networks TNODE:用于安全无线网络的低功耗传感器节点处理器
2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675259
G. Panic, O. Schrape, T. Basmer, F. Vater, K. Tittelbach-Helmrich
{"title":"TNODE: A low power sensor node processor for secure wireless networks","authors":"G. Panic, O. Schrape, T. Basmer, F. Vater, K. Tittelbach-Helmrich","doi":"10.1109/ISSoC.2013.6675259","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675259","url":null,"abstract":"In this paper we describe a sensor node crypto processor designed for use in wireless sensor networks with strong security demands. The presented system-on-chip is a mixed-signal processor-based design containing the hardware crypto accelerators (AES, ECC, SHA-1) that provide the means for secure communication in the network. The unique system architecture combines an asynchronous processor core with synchronous peripherals resulting in a low-power system operation. The designed chip integrates an embedded Flash memory and a 12-bit ADC making it a suitable solution for small-size sensor node devices. The paper describes the chip architecture and discusses the most important implementation and verification issues. Finally, the results of the chip measurement have been presented.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121030621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Dependency analysis and visualization tool for Kactus2 IP-XACT design framework 依赖性分析和可视化工具Kactus2 IP-XACT设计框架
2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675261
J. Määttä, Mikko Honkonen, Tommi Korhonen, E. Salminen, T. Hämäläinen
{"title":"Dependency analysis and visualization tool for Kactus2 IP-XACT design framework","authors":"J. Määttä, Mikko Honkonen, Tommi Korhonen, E. Salminen, T. Hämäläinen","doi":"10.1109/ISSoC.2013.6675261","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675261","url":null,"abstract":"Large-scale HW and SW projects contain thousands of source files, which requires proper file management in order to keep track of changes and keep the code in compilable state. Different parts of the system depend on each other, and even a small change in a certain part of the code may break the other parts. Dependency analysis can be used to prevent such problems by visualizing the SW structure so that dependencies are easily seen by the developer. This paper presents a novel tool for file dependency and change analysis and visualization that was implemented into our IP-XACT based Kactus2 design environment (GPL2). The tool is capable of sorting source files into IP-XACT file sets, extracting and visualizing file dependencies, and keeping track of changed files. It also offers the ability to create manual dependencies, e.g., between source code and documentation. The dependency and change analysis of 1k source code files containing 140k lines of code is performed in less than two minutes.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127283619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Implementation and evaluation of configuration scrubbing on CGRAs: A case study 在CGRAs上实现和评估配置洗涤:一个案例研究
2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675262
Syed M. A. H. Jafri, S. Piestrak, A. Hemani, K. Paul, J. Plosila, H. Tenhunen
{"title":"Implementation and evaluation of configuration scrubbing on CGRAs: A case study","authors":"Syed M. A. H. Jafri, S. Piestrak, A. Hemani, K. Paul, J. Plosila, H. Tenhunen","doi":"10.1109/ISSoC.2013.6675262","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675262","url":null,"abstract":"This paper investigates the overhead imposed by various configuration scrubbing techniques used in fault-tolerant Coarse Grained Reconfigurable Arrays (CGRAs). Today, reconfigurable architectures host large configuration memories. As we progress further in the nanometer regime, these configuration memories have become increasingly susceptible to single event upsets caused e.g. by cosmic radiation. Configuration scrubbing is a frequently used technique to protect these configuration memories against single event upsets. Existing works on configuration scrubbing deal only with FPGA without any reference to the CGRAs (in which configuration memories consume up to 50% of silicon area). Moreover, in the known literature lacks a comprehensive comparison of various configuration scrubbing techniques to guide system designers about the merits/demerits of different scrubbing methods which could be applied to CGRAs. To address these problems, in this paper we classify various configuration scrubbing techniques and quantify their trade-offs when implemented on a CGRA. Synthesis results reveal that scrubbing logic incurs negligible silicon overhead (up to 3% of the area of computational units). Simulation results obtained for a few algorithms/applications (FFT, FIR, matrix multiplication, and WLAN) show that the choice of the configuration scrubbing scheme (external vs. internal) has significant impact on both the size of configuration memory and the number of reconfiguration cycles (respectively 20-80% more and up to 38 times more for the former).","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131233224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Extending IP-XACT to embedded system HW/SW integration 将IP-XACT扩展到嵌入式系统软硬件集成
2013 International Symposium on System on Chip (SoC) Pub Date : 2013-12-02 DOI: 10.1109/ISSoC.2013.6675264
Antti Kamppi, Lauri Matilainen, J. Määttä, E. Salminen, T. Hämäläinen
{"title":"Extending IP-XACT to embedded system HW/SW integration","authors":"Antti Kamppi, Lauri Matilainen, J. Määttä, E. Salminen, T. Hämäläinen","doi":"10.1109/ISSoC.2013.6675264","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675264","url":null,"abstract":"Typical MPSoC FPGA product design is a rigid waterfall process proceeding one-way from HW to SW design. Any changes to HW trigger the SW project re-creation from the beginning. When several product variations or speculative development time exploration is required, the disk bloats easily with hundreds of Board Support Package (BSP), configuration and SW project files. In this paper, we present an IP-XACT based design flow that solves the problems by agile re-use of HW and SW components, automation and single golden reference source for information. We also present new extensions to IP-XACT since the standard lacks SW related features. Three use cases demonstrate how the BSP is changed, an application is moved to another processor and a function is moved from SW implementation to a HW accelerator. Our flow reduces the design time to one third compared to the conventional FPGA flow, the number of automated design phases is doubled and any manual error prone data transfer between HW and SW tools is completely avoided.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116814438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Proactive Thermal-Budget-Based Beltway Routing algorithm for thermal-aware 3D NoC systems 基于热感知3D NoC系统的主动热预算环城公路路由算法
2013 International Symposium on System on Chip (SoC) Pub Date : 2013-10-01 DOI: 10.1109/ISSoC.2013.6675281
Che-Chuan Kuo, Kun-Chih Chen, En-Jui Chang, A. Wu
{"title":"Proactive Thermal-Budget-Based Beltway Routing algorithm for thermal-aware 3D NoC systems","authors":"Che-Chuan Kuo, Kun-Chih Chen, En-Jui Chang, A. Wu","doi":"10.1109/ISSoC.2013.6675281","DOIUrl":"https://doi.org/10.1109/ISSoC.2013.6675281","url":null,"abstract":"The thermal problems of three-dimensional Network-on-Chip (3D NoC) systems become more serious because of die stacking. Besides, for high-performance requirement, the minimal adaptive routing algorithms result in unbalanced traffic load and worse temperature distribution in the system. On the other hand, the conventional selection strategies determine the routing path based on the traffic information, which leads to unawareness of the potential thermal hotspot and huge performance impact. To solve the problems, in this paper, we first define a novel thermal-aware routing index, Mean Time To Throttle (MTTT), which represents the remaining active time of the node before the temperature achieves the alarming level. Based on the information of MTTT, we propose a Proactive Thermal-Budget-Based Beltway Routing (PTB3R) to balance the temperature distribution of the NoC system. The experimental results show that the proposed PTB3R can help to reduce the number of throttled nodes by 25.56%~86.95% and improve network throughput by around 15.04%~19.87%.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121982074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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