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Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)最新文献

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An associative self-compacting buffer for communication switches 一种用于通信开关的联合自压缩缓冲器
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833609
J. Delgado-Frías, A. Jafri
{"title":"An associative self-compacting buffer for communication switches","authors":"J. Delgado-Frías, A. Jafri","doi":"10.1109/MMICA.1999.833609","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833609","url":null,"abstract":"This paper describes a novel VLSI CMOS implementation of a self-compacting buffer (SCB) for the dynamically allocated multi-queue (DAMQ) switch architecture. The SCB scheme dynamically allocates data regions within the input buffer for each output channel. The proposed scheme provides a high-performance solution to buffered communication switches that are required in interconnection networks. This performance comes from the DAMQ approach as well as the Associative Channel Pointer implementation and novel circuitry. The major components of the SCB are described in detail in this paper. The system has the capability of performing a read, a write, or a simultaneous read/write operation per cycle.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"92 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131770820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Harmonic distortion in fully-differential switched-current sigma-delta modulators 全差分开关电流σ - δ调制器的谐波畸变
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833617
J. M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río, Á. Rodríguez-Vázquez
{"title":"Harmonic distortion in fully-differential switched-current sigma-delta modulators","authors":"J. M. de la Rosa, B. Pérez-Verdú, F. Medeiro, R. del Río, Á. Rodríguez-Vázquez","doi":"10.1109/MMICA.1999.833617","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833617","url":null,"abstract":"This paper presents a systematic analysis of the harmonic distortion in /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) implemented with fully-differential switched-current (SI) circuits. Closed form expressions are derived for the third-order harmonic distortion in lowpass and bandpass /spl Sigma//spl Delta/Ms. For the latter, the third-order intermodulation distortion is also deduced. Time domain behavioral simulations validate our approach.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124847334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multigrate and dividate: two new arithmetic operations 乘除:两个新的算术运算
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833601
E. Kleihorst
{"title":"Multigrate and dividate: two new arithmetic operations","authors":"E. Kleihorst","doi":"10.1109/MMICA.1999.833601","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833601","url":null,"abstract":"As a counterpart of the integration and differentiation processes, it is logical to extend the mathematics with two operations along the same lines as summation, subtraction, multiplication and division. These two new operations the author has called multigration and dividation. In order to get a proper understanding of these two operations, a start is made with multigration. Dividation is the inverse operation.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114812516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-voltage, multibit sigma-delta modulator for wideband applications 用于宽带应用的低电压、多比特σ - δ调制器
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833618
H. Lampinen, O. Vainio
{"title":"A low-voltage, multibit sigma-delta modulator for wideband applications","authors":"H. Lampinen, O. Vainio","doi":"10.1109/MMICA.1999.833618","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833618","url":null,"abstract":"A low-voltage, multibit, fourth-order sigma-delta modulator circuit for wideband applications is implemented using a 0.35 /spl mu/m CMOS technology. The high-speed operation is achieved utilizing pipelining in the modulator architecture, well optimized complementary folded cascode feedforward compensated OTAs, and specific clocking strategies. The low-voltage operation is achieved by using proper circuit structures and optimized component sizes. The size of the modulator is 1.3/spl times/1.0 mm/sup 2/.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116798061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A tool for complete small-signal analytical modeling of large analog circuits 一个完整的大模拟电路的小信号分析建模工具
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833589
J. D. Rodríguez-García, O. Guerra, E. Roca, F. Fernández, Á. Rodríguez-Vázquez
{"title":"A tool for complete small-signal analytical modeling of large analog circuits","authors":"J. D. Rodríguez-García, O. Guerra, E. Roca, F. Fernández, Á. Rodríguez-Vázquez","doi":"10.1109/MMICA.1999.833589","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833589","url":null,"abstract":"This paper introduces a symbolic analyzer, which, based on the combination of simplification techniques, hierarchical and pole/zero analysis, enables the approximated symbolic analysis of large analog circuits.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128300715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A multiplier-free digital RMS calculation unit for integrated microsystems 用于集成微系统的无乘法器数字均方根计算单元
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833630
A. Daglio, P. Malcovati, F. Maleberti
{"title":"A multiplier-free digital RMS calculation unit for integrated microsystems","authors":"A. Daglio, P. Malcovati, F. Maleberti","doi":"10.1109/MMICA.1999.833630","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833630","url":null,"abstract":"This paper presents a novel 13-bit digital RMS calculation unit, specifically designed to be integrated together with sensor and interface circuits in complete microsystems. The circuit exploits oversampling techniques (bitstream processing) to eliminate the area inefficient multipliers required in traditional RMS calculation units. The proposed approach leads to a significant reduction (almost 30%) in the silicon area required to implement the RMS calculation algorithm for a 13 bit word.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125289962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Electronic model of a neuronal sinapsis of voltage to frequency, and frequency to voltage conversion 电压到频率和频率到电压转换的神经元突触的电子模型
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833627
J.L. Perez S., A. Garces, S. Quintana, A. Herrera, M. Banuelos, J. Castillo, W. Martinez, A. Padrón
{"title":"Electronic model of a neuronal sinapsis of voltage to frequency, and frequency to voltage conversion","authors":"J.L. Perez S., A. Garces, S. Quintana, A. Herrera, M. Banuelos, J. Castillo, W. Martinez, A. Padrón","doi":"10.1109/MMICA.1999.833627","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833627","url":null,"abstract":"In this work we present the results of a study of neurons with synapses of the frequency-voltage type response, and the effects of the autosynapse that give us responses of long period. We also present the effects of synapse frequency/voltage-voltage/frequency in the phenomena of autosynapse in neuron cascades. We also studied the effects of the time constant involved in the synapses and their effects on the response of the neurons, in the autosynapse as well as in the neuron oscillatory cascades. All the studies in this first approximation were accomplished with electronic circuits that model the neurons and its synapses.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131197054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Algorithm for phase accumulator synthesis for applications in DDS 用于DDS的相位累加器合成算法
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833637
R. Romero-Troncoso, G. Espinosa-Flores-Verdad
{"title":"Algorithm for phase accumulator synthesis for applications in DDS","authors":"R. Romero-Troncoso, G. Espinosa-Flores-Verdad","doi":"10.1109/MMICA.1999.833637","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833637","url":null,"abstract":"An algorithm for area-speed optimization in phase accumulator synthesis is presented here. Digital Direct Synthesis (DDS) requires an efficient phase accumulator as its main functional block. However, fast phase accumulators are very area demanding and the trade-off between area and speed is very critical. Implementation of phase accumulators with FPGA's and/or ASIC's should consider the approach presented here for optimization and synthesis.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"297 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131639600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Educational architecture LAN/CAN for process control engineering 用于过程控制工程的教育体系结构LAN/CAN
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833635
J. Fuertes, L. Vazquez, L. Rojas
{"title":"Educational architecture LAN/CAN for process control engineering","authors":"J. Fuertes, L. Vazquez, L. Rojas","doi":"10.1109/MMICA.1999.833635","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833635","url":null,"abstract":"Multiprotocol systems have been developed based on field bus technology connected to the university's LAN. The basic parts are PC and two CAN nodes. The PC interfaces the CAN nodes in the process control laboratory and the computer centre by a LAN. The hardware consists of: development card using Intel microcontroller 87c196, the SJA1000 CAN controller and the PCA 82c250 transceiver. The software to program 87c196 is performed in C and assembler language. The communication between the PC and the CAN node is based on the RS232 serial communication standard. As data server in one case and as remote controller-supervisor in the other, the PC is programmed in the C++ Builder language.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125073290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A dynamic dither /spl Sigma//spl Delta/ ADC with 103 dB DR for audio applications 动态抖动/spl Sigma//spl Delta/ ADC, DR值为103 dB，适用于音频应用
Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) Pub Date : 1999-07-26 DOI: 10.1109/MMICA.1999.833616
G. Gómez
{"title":"A dynamic dither /spl Sigma//spl Delta/ ADC with 103 dB DR for audio applications","authors":"G. Gómez","doi":"10.1109/MMICA.1999.833616","DOIUrl":"https://doi.org/10.1109/MMICA.1999.833616","url":null,"abstract":"A sigma-delta Analog to Digital Converter (ADC) using dynamic dither to achieve a tone-free Dynamic Range (DR) of 103 dB in an audio bandwidth is presented. The design was implemented using a 3rd order 2-1 cascade architecture with an oversampling ratio of 128. The ADC modulator consumes 22 mW from a 3.0 V power supply and was fabricated in 0.6 /spl mu/m CMOS (analog portion) and 0.3 /spl mu/m CMOS (digital portion) using Multi-Chip-Module (MCM) technology.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129711895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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