12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)最新文献

Surfing interconnect 冲浪互连

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06) Pub Date : 2006-03-13 DOI: 10.1109/ASYNC.2006.28

M. Greenstreet, Jihong Ren

引用次数: 20

ATRS: an alternative roadmap for semiconductors, technology evolution and impacts on system architecture ATRS:半导体、技术演进和对系统架构的影响的替代路线图

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06) Pub Date : 2006-03-13 DOI: 10.1109/ASYNC.2006.13

J. Schoellkopf

{"title":"ATRS: an alternative roadmap for semiconductors, technology evolution and impacts on system architecture","authors":"J. Schoellkopf","doi":"10.1109/ASYNC.2006.13","DOIUrl":"https://doi.org/10.1109/ASYNC.2006.13","url":null,"abstract":"Summary form only given. The recent evolution of semiconductor technology, in the last decades, brought tremendous improvements in performance increase at decreasing prices, perfectly following the famous Moore's law. Lithography is still improving and allows 0.7times linear shrink per technology node. However, many products are hitting the \"power wall\"! Silicon is free, but peak power consumption, power density, heat dissipation are preventing a straight usage of the available silicon area. The simple shrink, even if it is a perfect way for cost reduction, does not support power density increase, and is not supported by packaging technology which does not scale as fast as silicon. On the other hand, scaling allows to double transistor count at each node at constant die size: then the challenge for tomorrow consists in improving performance while maintaining a reasonable power consumption. Architects and designers must improve MOPS/Watt. In the old times, VDD was scaled by 0.7, so there was enough room to increase both complexity and clock frequency. This talk presents an \"alternative roadmap\" which is proposing a way to maintain power consumption stable (from today and forever): increase complexity as much as allowed by lithography, implementing a lot of parallelism at decreased clock frequency, with a moderate VDD scaling. There is a big impact on parallel architectures, memory hierarchy, and a bigger impact on device characteristics. We'll demonstrate that device performance must be relaxed compared to the ITRS roadmap, allowing to handle the leakage power crisis and to manage the huge problems due to technology variations. Low frequency and/or asynchronous operating modes are seen as mandatory ways for power management","PeriodicalId":221135,"journal":{"name":"12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115822385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An asynchronous high-throughput control circuit for proximity communication 用于近距离通信的异步高吞吐量控制电路

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06) Pub Date : 2006-03-13 DOI: 10.1109/ASYNC.2006.8

J. Ebergen, A. Chow, B. Coates, Justin Schauer, D. Hopkins

引用次数: 3

Asynchronous design: an enabler for flexible microelectronics 异步设计:柔性微电子的推动者

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06) Pub Date : 2006-03-13 DOI: 10.1109/ASYNC.2006.11

Nobuo Karaki

{"title":"Asynchronous design: an enabler for flexible microelectronics","authors":"Nobuo Karaki","doi":"10.1109/ASYNC.2006.11","DOIUrl":"https://doi.org/10.1109/ASYNC.2006.11","url":null,"abstract":"Summary form only given. Flexible microelectronics technology featuring low-temperature polysilicon (LTPS) TFT and surface free technology by laser annealing and ablation (SUFTLAR) is expected to become a platform for developing thin, flexible and low-cost display devices. LTPS TFTs are good for realizing large area displays and integrated circuits at lower cost. A drawback of LTPS TFTs, however, is that they have substantial deviations in characteristics, which are caused by deviations mainly in crystal grain size and thickness of silicon-oxide. Until now, these deviations were considered to be beyond the capability of synchronous circuit design, especially for large-scale circuits such as microprocessors driven by global clocking. Since asynchronous circuits are \"self-timed\", they absorb the deviations of device characteristics. Plus they run as faster as possible in event-driven fashion dissipating less power, and remain on standby for quick service. Even with the benefits of asynchronous circuits, it is considered difficult to proceed with circuit design using syntax-directed translation using VLSI programming languages such as CSP, Tangram and OCCAM, syntax of which is far from the standard HDL. The authors then decided to develop Verilog+ that comprises a subset of Verilog HDLR and minimal primitives used for describing the communications between processes. Flexible 8-bit asynchronous microprocessor ACT11 is the first successful instance of asynchronous design using Verilog+ without knowledge of element and wire delay except for datapath","PeriodicalId":221135,"journal":{"name":"12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114767536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

A novel design method for asynchronous bundled-data transfer circuits considering characteristics of delay variations 一种考虑延迟变化特性的异步数据传输电路设计新方法

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06) Pub Date : 2006-03-13 DOI: 10.1109/ASYNC.2006.6

Masashi Imai, T. Nanya

引用次数: 8

Multiple-rail phase-encoding for NoC NoC的多轨相位编码

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06) Pub Date : 2006-03-13 DOI: 10.1109/ASYNC.2006.23

C. D'Alessandro, D. Shang, A. Bystrov, A. Yakovlev, O. Maevsky

引用次数: 20

Measuring deep metastability 测量深部亚稳态

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06) Pub Date : 2006-03-13 DOI: 10.1109/ASYNC.2006.21

D. Kinniment, K. Heron, G. Russell

引用次数: 35

An ultra-low energy asynchronous processor for wireless sensor networks 用于无线传感器网络的超低能耗异步处理器

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06) Pub Date : 2006-03-13 DOI: 10.1109/ASYNC.2006.9

L. Necchi, L. Lavagno, D. Pandini, Laura Vanzago

引用次数: 30

Low-overhead testing of delay faults in high-speed asynchronous pipelines 高速异步管道延迟故障的低负荷测试

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06) Pub Date : 2006-03-13 DOI: 10.1109/ASYNC.2006.20

Gennette Gill, Ankur Agiwal, Montek Singh, Feng Shi, Y. Makris

引用次数: 23

Slack matching asynchronous designs 松散匹配异步设计

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06) Pub Date : 2006-03-13 DOI: 10.1109/ASYNC.2006.26

P. Beerel, Nam-Hoon Kim, Andrew Lines, Mike Davies

引用次数: 88