Asynchronous design: an enabler for flexible microelectronics

Nobuo Karaki
{"title":"Asynchronous design: an enabler for flexible microelectronics","authors":"Nobuo Karaki","doi":"10.1109/ASYNC.2006.11","DOIUrl":null,"url":null,"abstract":"Summary form only given. Flexible microelectronics technology featuring low-temperature polysilicon (LTPS) TFT and surface free technology by laser annealing and ablation (SUFTLAR) is expected to become a platform for developing thin, flexible and low-cost display devices. LTPS TFTs are good for realizing large area displays and integrated circuits at lower cost. A drawback of LTPS TFTs, however, is that they have substantial deviations in characteristics, which are caused by deviations mainly in crystal grain size and thickness of silicon-oxide. Until now, these deviations were considered to be beyond the capability of synchronous circuit design, especially for large-scale circuits such as microprocessors driven by global clocking. Since asynchronous circuits are \"self-timed\", they absorb the deviations of device characteristics. Plus they run as faster as possible in event-driven fashion dissipating less power, and remain on standby for quick service. Even with the benefits of asynchronous circuits, it is considered difficult to proceed with circuit design using syntax-directed translation using VLSI programming languages such as CSP, Tangram and OCCAM, syntax of which is far from the standard HDL. The authors then decided to develop Verilog+ that comprises a subset of Verilog HDLR and minimal primitives used for describing the communications between processes. Flexible 8-bit asynchronous microprocessor ACT11 is the first successful instance of asynchronous design using Verilog+ without knowledge of element and wire delay except for datapath","PeriodicalId":221135,"journal":{"name":"12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASYNC.2006.11","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12

Abstract

Summary form only given. Flexible microelectronics technology featuring low-temperature polysilicon (LTPS) TFT and surface free technology by laser annealing and ablation (SUFTLAR) is expected to become a platform for developing thin, flexible and low-cost display devices. LTPS TFTs are good for realizing large area displays and integrated circuits at lower cost. A drawback of LTPS TFTs, however, is that they have substantial deviations in characteristics, which are caused by deviations mainly in crystal grain size and thickness of silicon-oxide. Until now, these deviations were considered to be beyond the capability of synchronous circuit design, especially for large-scale circuits such as microprocessors driven by global clocking. Since asynchronous circuits are "self-timed", they absorb the deviations of device characteristics. Plus they run as faster as possible in event-driven fashion dissipating less power, and remain on standby for quick service. Even with the benefits of asynchronous circuits, it is considered difficult to proceed with circuit design using syntax-directed translation using VLSI programming languages such as CSP, Tangram and OCCAM, syntax of which is far from the standard HDL. The authors then decided to develop Verilog+ that comprises a subset of Verilog HDLR and minimal primitives used for describing the communications between processes. Flexible 8-bit asynchronous microprocessor ACT11 is the first successful instance of asynchronous design using Verilog+ without knowledge of element and wire delay except for datapath
异步设计:柔性微电子的推动者
只提供摘要形式。以低温多晶硅(LTPS) TFT和激光退火烧蚀(SUFTLAR)无表面技术为特色的柔性微电子技术有望成为开发薄、柔性和低成本显示器件的平台。LTPS tft可以较低的成本实现大面积显示和集成电路。然而,LTPS tft的一个缺点是它们的特性有很大的偏差,这主要是由氧化硅的晶粒尺寸和厚度的偏差引起的。到目前为止,这些偏差被认为超出了同步电路设计的能力,特别是对于大规模电路,如由全局时钟驱动的微处理器。由于异步电路是“自定时”的,它们吸收了器件特性的偏差。此外,它们以事件驱动的方式尽可能快地运行,消耗更少的功率,并保持待机状态,以便快速服务。即使具有异步电路的优点,使用诸如CSP, Tangram和OCCAM等VLSI编程语言使用语法定向翻译进行电路设计也被认为是困难的,这些语言的语法与标准HDL相差甚远。然后,作者决定开发Verilog+,它包含Verilog HDLR的一个子集和用于描述进程之间通信的最小原语。灵活的8位异步微处理器ACT11是使用Verilog+进行异步设计的第一个成功实例,无需了解除数据路径外的元件和线延迟
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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