{"title":"Asynchronous design: an enabler for flexible microelectronics","authors":"Nobuo Karaki","doi":"10.1109/ASYNC.2006.11","DOIUrl":null,"url":null,"abstract":"Summary form only given. Flexible microelectronics technology featuring low-temperature polysilicon (LTPS) TFT and surface free technology by laser annealing and ablation (SUFTLAR) is expected to become a platform for developing thin, flexible and low-cost display devices. LTPS TFTs are good for realizing large area displays and integrated circuits at lower cost. A drawback of LTPS TFTs, however, is that they have substantial deviations in characteristics, which are caused by deviations mainly in crystal grain size and thickness of silicon-oxide. Until now, these deviations were considered to be beyond the capability of synchronous circuit design, especially for large-scale circuits such as microprocessors driven by global clocking. Since asynchronous circuits are \"self-timed\", they absorb the deviations of device characteristics. Plus they run as faster as possible in event-driven fashion dissipating less power, and remain on standby for quick service. Even with the benefits of asynchronous circuits, it is considered difficult to proceed with circuit design using syntax-directed translation using VLSI programming languages such as CSP, Tangram and OCCAM, syntax of which is far from the standard HDL. The authors then decided to develop Verilog+ that comprises a subset of Verilog HDLR and minimal primitives used for describing the communications between processes. Flexible 8-bit asynchronous microprocessor ACT11 is the first successful instance of asynchronous design using Verilog+ without knowledge of element and wire delay except for datapath","PeriodicalId":221135,"journal":{"name":"12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASYNC.2006.11","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
Summary form only given. Flexible microelectronics technology featuring low-temperature polysilicon (LTPS) TFT and surface free technology by laser annealing and ablation (SUFTLAR) is expected to become a platform for developing thin, flexible and low-cost display devices. LTPS TFTs are good for realizing large area displays and integrated circuits at lower cost. A drawback of LTPS TFTs, however, is that they have substantial deviations in characteristics, which are caused by deviations mainly in crystal grain size and thickness of silicon-oxide. Until now, these deviations were considered to be beyond the capability of synchronous circuit design, especially for large-scale circuits such as microprocessors driven by global clocking. Since asynchronous circuits are "self-timed", they absorb the deviations of device characteristics. Plus they run as faster as possible in event-driven fashion dissipating less power, and remain on standby for quick service. Even with the benefits of asynchronous circuits, it is considered difficult to proceed with circuit design using syntax-directed translation using VLSI programming languages such as CSP, Tangram and OCCAM, syntax of which is far from the standard HDL. The authors then decided to develop Verilog+ that comprises a subset of Verilog HDLR and minimal primitives used for describing the communications between processes. Flexible 8-bit asynchronous microprocessor ACT11 is the first successful instance of asynchronous design using Verilog+ without knowledge of element and wire delay except for datapath