2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)最新文献_第2页

A Generalized Fluid Approximation for analysis of an integrated service system 综合服务系统分析的广义流体近似

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602292

Yue-Cai Huang, K. Ko, M. Zukerman

引用次数: 2

Energy efficient routing algorithms in dynamic optical core networks with dual energy sources 双能量源动态光核心网的高能效路由算法

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602299

Jiayuan Wang, A. M. Fagertun, S. Ruepp, L. Dittmann

引用次数: 4

Load-balanced Birkhoff-von Neumann switches and fat-tree networks 负载均衡Birkhoff-von Neumann交换机和胖树网络

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602304

Hung-Shih Chueh, Ching-Ming Lien, Cheng-Shang Chang, Jay Cheng, D. Lee

{"title":"Load-balanced Birkhoff-von Neumann switches and fat-tree networks","authors":"Hung-Shih Chueh, Ching-Ming Lien, Cheng-Shang Chang, Jay Cheng, D. Lee","doi":"10.1109/HPSR.2013.6602304","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602304","url":null,"abstract":"Fat-tree networks have been widely used in the field of Network-on-Chip. One of the key issues in a fat-tree network is that the degree of a node has to be increased rapidly from the bottom of the tree to the root. As such, the complexity of implementing the switches near the root could be extremely high, and this poses a serious scalability issue. To cope with the scalability issue in fat-tree networks, many previous works require changing the tree topology and adding buffers in nodes. Unlike the existing arts, we adopt a different approach that can still maintain the original tree topology without adding any buffers in internal nodes. Our key idea is to explore various nice features of the load-balanced Birkhoff-von Neumann switches. Such switches have been shown to achieve 100% throughput for all admissible traffic and have comparable delay performance to the ideal output-buffered switch when traffic is heavy and bursty. We show that the implementation complexity can be greatly reduced if a fat-tree network is only required to realize a set of N permutations needed for the N × N load-balanced Birkhoff-von Neumann switches. For this, we first derive a lower bound on the required degree for each node in a fat-tree network. By using the uniform mapping property of the bit-reverse permutation, we show that there exists a set of N permutations that achieve the lower bound.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126696864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Power-efficient connection provisioning with traffic splitting in IP over WDM networks 在IP over WDM网络中使用流量分割的高能效连接配置

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602320

Gaofeng Wu, G. Mohan

引用次数: 1

Dynamic bandwidth allocation with QoS support for integrated EPON/WiMAX networks 支持QoS的EPON/WiMAX集成网络的动态带宽分配

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602293

Hui-Tang Lin, Chai-Lin Lai, Yu-Chih Huang

{"title":"Dynamic bandwidth allocation with QoS support for integrated EPON/WiMAX networks","authors":"Hui-Tang Lin, Chai-Lin Lai, Yu-Chih Huang","doi":"10.1109/HPSR.2013.6602293","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602293","url":null,"abstract":"The integration of EPON and WiMAX access networks has demonstrated considerable promise as an access solution applicable to the architecture of Fixed Mobile Convergence (FMC). The complementary features of these two systems provide high bandwidth and mobility, while reducing network deployment costs. Despite the fact that many network hardware architectures have been proposed for integrated EPON/WiMAX networks, the issue of bandwidth allocation for heterogeneous traffic (WiMAX and Ethernet) remains unresolved. This study proposes a novel Dynamic Bandwidth Allocation (DBA) scheme, under which the discrete network protocols of WiMAX and EPON access networks can run concurrently and efficiently. The proposed DBA mechanism adopts a framed approach, in which the time domains in both the optical and wireless access networks are partitioned into successive fixed-length frames. Within each frame, heterogeneous traffic is synchronously transmitted in the optical and wireless domains, and sufficient network resources are provided to ensure the respective Quality of Service (QoS) requirements of WiMAX and Ethernet traffic. Simulation results confirm the effectiveness and efficiency of the proposed DBA mechanism.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123483248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Parallel prioritized flow scheduling for software defined data center network 软件定义数据中心网络并行优先流调度

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602317

Bo-Yu Ke, Po-Long Tien, Yu-Lin Hsiao

引用次数: 10

Traffic engineering of high-rate large-sized flows 高速大流量交通工程

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602302

Tian Jin, Chris Tracy, M. Veeraraghavan, Zhenzhen Yan

{"title":"Traffic engineering of high-rate large-sized flows","authors":"Tian Jin, Chris Tracy, M. Veeraraghavan, Zhenzhen Yan","doi":"10.1109/HPSR.2013.6602302","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602302","url":null,"abstract":"High-rate large-sized (α) flows have adverse effects on delay-sensitive flows. Research-and-education network providers are interested in identifying such flows within their networks, and directing these flows to traffic-engineered QoS-controlled virtual circuits. To achieve this goal, a design is proposed for a hybrid network traffic engineering system (HNTES) that would run on an external server, gather NetFlow reports from routers, analyze these reports to identify α-flow source/destination address prefixes, configure firewall filter rules at ingress routers to extract future flows and redirect them to previously provisioned intra-domain virtual circuits. This paper presents an evaluation of this HNTES design using NetFlow reports collected over a 7-month period from four ESnet routers. Our analysis shows that had HNTES been deployed, it would have been highly effective, e.g., > 90% of α-bytes that arrived at the four routers over the 7-month period would have been redirected to virtual circuits. Design aspects such as whether to use /24 subnet IDs or /32 addresses in firewall filters, and which router interfaces' NetFlow reports to include in the HNTES analysis, are studied.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130853845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

GPU-accelerated hash and wildcard hybrid flow switching for tackling massive flow entries gpu加速散列和通配符混合流切换，用于处理大量流条目

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602315

N. Matsumoto, M. Hayashi, I. Morita

引用次数: 3

Multi-match packet classification on memory-logic trade-off FPGA-based architecture 基于内存-逻辑权衡的fpga多匹配数据包分类

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602301

C. Zerbini, J. Finochietto

{"title":"Multi-match packet classification on memory-logic trade-off FPGA-based architecture","authors":"C. Zerbini, J. Finochietto","doi":"10.1109/HPSR.2013.6602301","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602301","url":null,"abstract":"Packet processing is becoming much more challenging as networks evolve towards a multi-service platform. In particular, packet classification demands smaller processing times as data rates increase. To successfully meet this requirement, hardware-based classification architectures have become an area of extensive research. Even if Field Programmable Logic Arrays (FPGAs) have emerged as an interesting technology for implementing these architectures, existing proposals either exploit maximal concurrency with unbounded resource consumption, or base the architecture on distributed RAM memory-based schemes which strongly undervalues FPGA capabilities. Moreover, most of these proposals target best-match classification and are not suited for high-speed updates of classification rulesets. In this paper, we propose a new approach which exploits rich logic resources available in modern FPGAs while reducing memory consumption. Our architecture is conceived for multi-match classification, and its mapping methodology is naturally suited for high-speed, simple updating of the classification ruleset. Analytical evaluation and implementation results of our architecture are promising, demonstrating that it is suitable for line speed processing whith balanced resource consumption. With additional optimizations, our proposal has the potential to be integrated into network procesing architectures demanding all aforementioned features.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124770223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Parallel prioritized scheduling for WDM optical switching system WDM光交换系统的并行优先调度

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602295

P. Tien, Bo-Yu Ke

{"title":"Parallel prioritized scheduling for WDM optical switching system","authors":"P. Tien, Bo-Yu Ke","doi":"10.1109/HPSR.2013.6602295","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602295","url":null,"abstract":"Packet scheduling for WDM optical switching systems requires exceedingly low latency processing, making it impractical to be realized by non-parallel based algorithms. In this paper, we propose a new recurrent discrete-time synchronous ranked neural-network (DSRN) for parallel prioritized scheduling. The DSRN is structured with ranked neurons and is capable of operating in a fully parallel (i.e., synchronous) discrete-time manner, and thus can be implemented in digital systems. We then design a DSRN scheduler for a previously proposed experimental WDM optical switching system (WOPIS). For newly arriving packets, the DSRN scheduler determines in real time an optimal set of input/output paths within WOPIS, achieving maximal throughput and priority differentiation subject to the switch- and buffer-contention-free constraints. We delineate via a theorem that DSRN will converge to the optimal solution. The theorem also provides a theoretical upper bound of the convergence latency, O(H), where H is the switch port count. Finally, we demonstrate that, via CUDA-based simulations, the DSRN scheduler achieves near-optimal throughput and prioritized scheduling, with nearly O(logH) convergence latency.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121251817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0