2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)最新文献

Circuit emulation in optical packet-switched WDM ring network for wireless backhaul 无线回程光分组交换WDM环网电路仿真

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602294

I. Chao, M. Yuang

引用次数: 0

On practical stable packet scheduling for bufferless three-stage Clos-network switches 无缓冲三级clos网络交换机的实用稳定分组调度

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602283

Yu Xia, H. J. Chao

{"title":"On practical stable packet scheduling for bufferless three-stage Clos-network switches","authors":"Yu Xia, H. J. Chao","doi":"10.1109/HPSR.2013.6602283","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602283","url":null,"abstract":"In this paper, we extend our previous work of StablePlus, a stable scheduling algorithm for single-stage packet switches, to bufferless three-stage Clos-network switches. StablePlus is based on an existing stable distributed scheduling algorithm, called DISQUO. We further improve the switching performance by incorporating a heuristic scheduling algorithm after the DISQUO scheduling. In a three-stage Clos-network switch, DISQUO is first used to solve the output contention which generates a stable matching between the input and output ports, then Karol's algorithm is used to find the feasible internal paths for the matched input and output pairs. However, the latter requires multiple mini-cycles to complete the path-finding task. Worse is that the number of mini-cycles increases as the switch size does, limiting the Clos-network to a small implementable size. By replacing the Hamiltonian Walk in DISQUO with time-division multiplexing (TDM) scheme, we show that the number of required mini-cycles for Karol's algorithm can be reduced to only two, independent of the switch size. Moreover, with the help of a parallel hardware approach, we can implement packet scheduling in O(1) time complexity. To support high data rates, e.g., 100 Gbps, we can also make the scheduling work on a frame basis. We prove that StablePlus can achieve 100% throughput under any admissible traffic, and by simulations we show that it also has good delay performance.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129934390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Adaptive forward error correction for energy efficient optical transport networks 节能光传输网络的自适应前向纠错

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602316

Anders Rasmussen, S. Ruepp, M. Berger, K. J. Larsen

引用次数: 1

A cross layer routing protocol in CRMANET CRMANET中的一种跨层路由协议

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602318

Y. Sun, C. Phillips, Jingwen Bai, Liumeng Song, Rina Wu

引用次数: 3

Interest flooding reduction in Content Centric Networks 减少内容中心网络中的兴趣泛滥

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602313

Vijayabharathi Ekambaram, K. Sivalingam

引用次数: 7

A low power and delay multi-protocol switch with IO and network virtualization 具有IO和网络虚拟化的低功耗和延迟多协议交换机

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602287

Haojun Luo, J. Hui, A. Fayoumi

{"title":"A low power and delay multi-protocol switch with IO and network virtualization","authors":"Haojun Luo, J. Hui, A. Fayoumi","doi":"10.1109/HPSR.2013.6602287","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602287","url":null,"abstract":"Data centers connect a larger number of servers requiring IO and switches with low power and delay. Virtualization of IO and network is crucial for these servers, which run virtual processes for computing, storage, and applications. We propose using the PCI Express (PCIe) protocol and a new PCIe switch fabric for IO and switch virtualization. The switch fabric has little data buffering, allowing up to 512 physical 10 Gb/s PCIe 2.0 lanes to be connected via a switch fabric on a chip. The switch is scalable with adapters running multiple adaptation protocols, such as Ethernet over PCIe, PCIe over Internet, or FibreChannel over Ethernet. Such adaptation protocols allow integration of IO often required for disjoint data center applications such as storage and networking. The novel switch fabric based on space-time carrier sensing facilitates high bandwidth, low power, and low delay multiprotocol switching. To achieve Terabit switching, both time (high transmission speed) and space (multi-stage interconnection network) technologies are required. In this paper, we present the design of an up to 256 lanes Close-network of multistage crossbar switch fabric for PCIe system. The switch core consists of 32 16x16 crossbar sub-switches. We also propose a new output contention resolution algorithm utilizing an out-of-band protocol of Request-To-Send (RTS), Clear-To-Send (CTS) before sending PCIe packets through the switch fabric. Preliminary power and delay estimates are provided.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"7 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131541211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Collector-based cell reordering in load-balanced switch fabrics 负载均衡交换结构中基于收集器的单元重排序

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602282

S. Antonakopoulos, S. Fortune, R. McLellan, Lisa Zhang

引用次数: 2

On capacity provisioning in datacenter networks for full bandwidth communication 关于在数据中心网络中为全带宽通信提供容量

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602291

Wenda Ni, Changcheng Huang, Jing Wu

引用次数: 1

N-Cloud: Improving performance and security in cloud storage N-Cloud:提高云存储的性能和安全性

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602319

Fahad Alsolami, C. E. Chow

引用次数: 15

PIE: A lightweight control scheme to address the bufferbloat problem PIE:解决缓冲区膨胀问题的轻量级控制方案

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602305

Rong Pan, P. Natarajan, C. Piglione, M. Prabhu, V. Subramanian, F. Baker, Bill VerSteeg

{"title":"PIE: A lightweight control scheme to address the bufferbloat problem","authors":"Rong Pan, P. Natarajan, C. Piglione, M. Prabhu, V. Subramanian, F. Baker, Bill VerSteeg","doi":"10.1109/HPSR.2013.6602305","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602305","url":null,"abstract":"Bufferbloat is a phenomenon where excess buffers in the network cause high latency and jitter. As more and more interactive applications (e.g. voice over IP, real time video conferencing and financial transactions) run in the Internet, high latency and jitter degrade application performance. There is a pressing need to design intelligent queue management schemes that can control latency and jitter; and hence provide desirable quality of service to users. We present here a lightweight design, PIE (Proportional Integral controller Enhanced), that can effectively control the average queueing latency to a reference value. The design does not require per-packet extra processing, so it incurs very small overhead and is simple to implement in both hardware and software. In addition, the design parameters are self-tuning, and hence PIE is robust and optimized for various network scenarios. Simulation results, theoretical analysis and Linux testbed results show that PIE can ensure low latency and achieve high link utilization under various congestion situations.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125785928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 362