2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)最新文献_第4页

Dynamic virtual routers using multiway segment tree 使用多路段树的动态虚拟路由器

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602308

Yeim-Kuan Chang, Zizhen Ou

引用次数: 0

Mesh router selection to maximize system throughput in dense Wireless Mesh Networks 网状路由器选择，以最大限度地提高系统吞吐量在密集的无线网状网络

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602300

Panu Avakul, Hiroki Nishiyama, N. Kato, Y. Shimizu, T. Kumagai

{"title":"Mesh router selection to maximize system throughput in dense Wireless Mesh Networks","authors":"Panu Avakul, Hiroki Nishiyama, N. Kato, Y. Shimizu, T. Kumagai","doi":"10.1109/HPSR.2013.6602300","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602300","url":null,"abstract":"Wireless Mesh Network (WMN) is a promising networking architecture because of its useful characteristics such as low deployment cost, ease of maintenance, network robustness and reliable coverage. Each node in the network is referred to either as Mesh Router (MR), Mesh Client (MC), or Mesh Gateway (MG) depending on its role in the network. MRs are interconnected to form a mesh backbone network, which can relay communications service from MCs to the MG. In many situations, MRs deployment are uncontrollable, and thus deployed MRs may not have ideal locations. In addition, in a dense network, using all available MRs that are deployed randomly to form mesh backbone network would results in a lower performance than what could be achieved. Therefore, our goal aims to select a set of working MRs that would yield an improved upper bound throughput, while still preserving connectivity. Our contributions include using graphs to represent multi-tier WMN and utilizing them to determine the set of MRs that can be safely removed from the network without severing any connectivity of the network. Furthermore, we proposed algorithm that goes through those set of MRs to determine the MRs which should be removed from the network to improve the overall performance, and we demonstrate capacity improvement brought by our scheme through simulations.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131905942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

TCAM-based high speed Longest prefix matching with fast incremental table updates 基于tcam的高速最长前缀匹配和快速增量表更新

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602288

Anders Rasmussen, A. Kragelund, M. Berger, H. Wessing, S. Ruepp

{"title":"TCAM-based high speed Longest prefix matching with fast incremental table updates","authors":"Anders Rasmussen, A. Kragelund, M. Berger, H. Wessing, S. Ruepp","doi":"10.1109/HPSR.2013.6602288","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602288","url":null,"abstract":"This paper presents a new TCAM-based method for determining the Longest Prefix Match (LPM) in an IP routing table. The method is based on modifying the address encoder of the standard TCAM design to take the prefix lengths of the IP routing entries into account while performing multi-match resolution, thus allowing prefixes to be inserted in any random order. This enables full utilization of the TCAM address space while greatly simplifying the updating procedure as complex software sorting algorithms and extensive table modifications are avoided. The result is faster table updates and consequently a higher throughput of the network search engine, since the TCAM down time caused by incremental updates is eliminated. The LPM scheme is described in HDL for FPGA implementation and compared to an existing scheme for customized CAM circuits. The paper shows that the proposed scheme can process more packets per second, has less per-lookup power consumption and is easier to expand to larger routing tables than the existing implementation. The latency of the LPM operation is only log2 N clock cycles, where N is the maximum number of prefixes in the TCAM, and in a pipelined implementation the throughput of the system is one Longest Prefix Match lookup per clock cycle.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132441608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

External monitoring of highly parallel network processors 高度并行网络处理器的外部监控

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602312

Xinming Chen, D. Chasaki, T. Wolf

引用次数: 5

SI-DFA: Sub-expression integrated Deterministic Finite Automata for Deep Packet Inspection 深度包检测的子表达式集成确定性有限自动机

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602307

A. Khalid, Rajat Sen, A. Chattopadhyay

{"title":"SI-DFA: Sub-expression integrated Deterministic Finite Automata for Deep Packet Inspection","authors":"A. Khalid, Rajat Sen, A. Chattopadhyay","doi":"10.1109/HPSR.2013.6602307","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602307","url":null,"abstract":"Finite automata is widely used for Deep Packet Inspection (DPI) of network traffic. Two types of automata employed for this purpose are Non-deterministic Finite Automata (NFA) and Deterministic Finite Automata (DFA). An NFA suffers from a large memory bandwidth per character due to multiple active states. A DFA, in comparison, ensures a linear processing time of O(1) for memory based architectures. However, the DFA state explosion conditions commonly occurring in today's NIDS rule-sets, render the automata with practically infeasible memory space requirements. To avoid state blowup we propose a semi-deterministic automata, Sub-expression Integrated DFA (SI-DFA), that ensures processing time of a single standard DFA. Rules are broken into sub-expressions at blowup conditions and compiled into a single DFA along with an association table, to correctly encapsulate equivalent automata. We list the rare cases in regular expressions for which sub-expression Integration is incorrect and present methodology to detect their occurrences. We evaluate SI-DFA on real-world rule-sets like Bro, Snort and Linux filters and compare their performance with the state-of-the-art hybrid automata solutions. SI-DFA renders a 66-97% reduction in processing bandwidth, up to 68% lower space requirement and an improvement trend with increasing rule complexity when compared to the traditional solutions.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130860349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Architecture and performance models for scalable IP lookup engines on FPGA FPGA上可扩展IP查找引擎的架构和性能模型

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602306

Y. Yang, Yun Qu, Swapnil Haria, V. Prasanna

{"title":"Architecture and performance models for scalable IP lookup engines on FPGA","authors":"Y. Yang, Yun Qu, Swapnil Haria, V. Prasanna","doi":"10.1109/HPSR.2013.6602306","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602306","url":null,"abstract":"We propose a unified methodology for optimizing IPv4 and IPv6 lookup engines based on the balanced range tree (BRTree) architecture on FPGA. A general BRTree-based IP lookup solution features one or more linear pipelines with a large and complex design space. To allow fast exploration of the design space, we develop a concise set of performance models to characterize the tradeoffs among throughput, table size, lookup latency, and resource requirement of the IP lookup engine. In particular, a simple but realistic model of DDR3 memory is used to accurately estimate the off-chip memory performance. The models are then utilized by the proposed methodology to optimize for high lookup rates, large prefix tables, and a fixed maximum lookup latency, respectively. In our prototyping scenarios, a state-of-the-art FPGA could support (1) up to 24 M IPv6 prefixes with 400 Mlps (million lookups per second); (2) up to 1.6 Blps (billion lookups per second) with 1.1 M IPv4 prefixes; and (3) up to 554 K IPv4 prefixes and 400 Mlps with a lookup latency bounded in 400 ns. All our designs achieve 5.6x - 70x the energy efficiency of TCAM, and have performance independent of the prefix distribution.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132911341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Minimizing scheduling complexity with a Clos-network space-space-memory (SSM) packet switch 使用Clos-network - space-space-memory (SSM)分组交换机最小化调度复杂性

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602284

Chuan-Bi Lin, R. Rojas-Cessa

引用次数: 3

OpenVRoute: An open architecture for high-performance programmable virtual routers OpenVRoute:高性能可编程虚拟路由器的开放架构

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602311

Z. Bozakov, Panagiotis Papadimitriou

{"title":"OpenVRoute: An open architecture for high-performance programmable virtual routers","authors":"Z. Bozakov, Panagiotis Papadimitriou","doi":"10.1109/HPSR.2013.6602311","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602311","url":null,"abstract":"In recent years network virtualization has emerged as an essential instrument for spurring innovation and consolidating resources. As a key technology, router virtualization enables the operation of multiple logical router instances within a single box. However, both commercial hardware solutions and PC-based software prototypes exhibit limitations in terms of programmability, memory, forwarding performance or port density. In this paper, we present OpenVRoute, an architecture that satisfies the requirements for router virtualization by combining the advantages of commodity switches and server hardware while mitigating their inherent shortcomings. Open-VRoute provides a transparent binding between the logical and physical router resources, using OpenFlow as a glue between the individual architecture components. OpenVRoute employs a split forwarding plane, caching high data-rate flows in an external OpenFlow switch while processing low-volume traffic in a software datapath hosted on a server. We exemplify the OpenVRoute architecture, and evaluate the performance and scalability of the main components.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128138821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Studies in applying PCA and wavelet algorithms for network traffic anomaly detection 应用PCA和小波算法进行网络流量异常检测的研究

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR) Pub Date : 2013-07-08 DOI: 10.1109/HPSR.2013.6602310

S. Novakov, Chung-Horng Lung, I. Lambadaris, N. Seddigh

{"title":"Studies in applying PCA and wavelet algorithms for network traffic anomaly detection","authors":"S. Novakov, Chung-Horng Lung, I. Lambadaris, N. Seddigh","doi":"10.1109/HPSR.2013.6602310","DOIUrl":"https://doi.org/10.1109/HPSR.2013.6602310","url":null,"abstract":"The rising complexity of network anomalies necessitates increased attention to developing new techniques for detecting those anomalies. The majority of current network and security monitoring tools utilize a signature-based approach to detect anomalies. This approach must be complemented with other methods to widen the coverage and speed of anomaly detection. In recent years, a great deal of effort has been spent on studying network traffic anomaly detection techniques by security researchers. Those techniques include the statistical analysis technique referred to as PCA (Principal Component Analysis), clustering and Wavelet-based spectral analysis of network traffic. This paper makes three key contributions to advance the state of the art in network traffic anomaly detection. First, we study the effectiveness of PCA and Wavelet algorithms in detecting network anomalies from a labeled data set known as Kyoto2006+ - providing a useful baseline for future researchers. Second, we propose a novel anomaly detection approach based on a hybrid PCA-Haar Wavelet analysis methodology. The hybrid approach uses PCA to describe the data and Haar Wavelet filtering for analysis. Finally, we study the impact of applying the techniques solely to flow-based traffic summary data to detect network anomalies. The experimental results demonstrate an improved accuracy of the hybrid approach in comparison with the two algorithms individually.","PeriodicalId":220418,"journal":{"name":"2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126119892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27