7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)最新文献_第4页

Integrating PSL properties into SystemC transactional modeling — Application to the verification of a modem SoC 将PSL属性集成到SystemC事务建模中——用于验证调制解调器SoC的应用

7th IEEE International Symposium on Industrial Embedded Systems (SIES'12) Pub Date : 2012-06-20 DOI: 10.1109/SIES.2012.6356588

L. Pierre, L. Ferro, Zeineb Bel Hadj Amor, Philippe Bourgon, J. Quévremont

引用次数: 8

Certification-cognizant scheduling of tasks with pessimistic frequency specification 具有悲观频率规范的任务认证认知调度

7th IEEE International Symposium on Industrial Embedded Systems (SIES'12) Pub Date : 2012-06-20 DOI: 10.1109/SIES.2012.6356567

Sanjoy Baruah

引用次数: 29

Non-generic floating-point software support for embedded media processing 支持嵌入式媒体处理的非通用浮点软件

7th IEEE International Symposium on Industrial Embedded Systems (SIES'12) Pub Date : 2012-06-20 DOI: 10.1109/SIES.2012.6356597

C. Jeannerod, Jingyan Jourdan-Lu, Christophe Monat

引用次数: 1

Embedded systems: Many cores — Many problems 嵌入式系统:许多核心-许多问题

7th IEEE International Symposium on Industrial Embedded Systems (SIES'12) Pub Date : 2012-06-20 DOI: 10.1109/SIES.2012.6356583

R. Wilhelm, J. Reineke

引用次数: 43

An LLVM-based hybrid binary translation system 基于llvm的混合二进制翻译系统

7th IEEE International Symposium on Industrial Embedded Systems (SIES'12) Pub Date : 2012-06-20 DOI: 10.1109/SIES.2012.6356589

Bor-Yeh Shen, Jyun-Yan You, Wuu Yang, W. Hsu

{"title":"An LLVM-based hybrid binary translation system","authors":"Bor-Yeh Shen, Jyun-Yan You, Wuu Yang, W. Hsu","doi":"10.1109/SIES.2012.6356589","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356589","url":null,"abstract":"Static binary translation (SBT) systems and dynamic binary translation (DBT) systems have their own merits and disadvantages. SBT can perform whole-program optimizations and do not incur run-time overheads. However, the code discovery and the code location problems caused by indirect branches make SBT systems hard to develop. On the other hand, DBT can perform optimizations based on program's runtime behaviors and can handle indirect branches easily. However, because the translation time accounts for a part of the execution time, DBT systems cannot perform aggressive optimizations. Therefore, quality of the code generated by DBT is not as good as that by SBT. In this paper, we present a hybrid binary translation (HBT) system which combines the merits of both SBT and DBT. It leverages the LLVM infrastructure to translate source binary code, optimize, and generate target binary code. It first translates binary statically. If a run-time exception happens, the HBT system switches to dynamic translation. On the EEMBC benchmark suite, our experimental result shows that the HBT system can run about 4 to 20 times faster than a LLVM-based DBT system.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"148 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130087220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Modeling uncertainties in safety-critical real-time systems: A probabilistic component-based analysis 安全关键实时系统中的不确定性建模:基于概率成分的分析

7th IEEE International Symposium on Industrial Embedded Systems (SIES'12) Pub Date : 2012-06-20 DOI: 10.1109/SIES.2012.6356582

D. Khan, L. Santinelli, L. Cucu-Grosjean

引用次数: 0

Combining instruction set simulation and WCET analysis for embedded software performance estimation 结合指令集仿真和WCET分析进行嵌入式软件性能评估

7th IEEE International Symposium on Industrial Embedded Systems (SIES'12) Pub Date : 2012-06-20 DOI: 10.1109/SIES.2012.6356600

Stefan Hauck-Stattelmann, Sebastian Ottlik, A. Viehl, O. Bringmann, W. Rosenstiel

{"title":"Combining instruction set simulation and WCET analysis for embedded software performance estimation","authors":"Stefan Hauck-Stattelmann, Sebastian Ottlik, A. Viehl, O. Bringmann, W. Rosenstiel","doi":"10.1109/SIES.2012.6356600","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356600","url":null,"abstract":"Simulation-based approaches to evaluate the functional and non-functional properties of embedded software are in widespread industrial use for design space exploration and virtual prototyping. As simulation performance is usually the main concern for these tools, they often lack an accurate timing model of the underlying processor. On the other hand, tools aimed at the worst-case execution time (WCET) analysis of embedded software contain accurate models for the timing behavior of embedded processors. Yet, these accurate processor models are only used to determine the worst-case path through the analyzed program. This paper proposes the combination of existing tools from both domains. The combination of an a priori analysis of machine code with a dynamic selection of basic block timing estimates during the execution of the program in a high-speed instruction set simulator (ISS) reduces the simulation overhead for cycle-accurate timing estimation. By keeping track of the execution history during execution of the analyzed software, the full accuracy of the offline performance model can be used without introducing pessimism to the simulation-based performance estimates. As most of the timing estimation is done before the simulation, only a slight decrease in simulation performance of the high-speed ISS can be expected.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131704009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

A formal support for homogeneous simulation of heterogeneous embedded systems 对异构嵌入式系统的同构仿真的正式支持

7th IEEE International Symposium on Industrial Embedded Systems (SIES'12) Pub Date : 2012-06-20 DOI: 10.1109/SIES.2012.6356587

L. D. Guglielmo, F. Fummi, G. Pravadelli, F. Stefanni, S. Vinco

引用次数: 8

Response time analysis for mixed messages in CAN supporting transmission abort requests 支持传输中止请求的CAN混合消息响应时间分析

7th IEEE International Symposium on Industrial Embedded Systems (SIES'12) Pub Date : 2012-06-20 DOI: 10.1109/SIES.2012.6356599

S. Mubeen, Jukka Mäki-Turja, Mikael Sjödin

引用次数: 12

Global schedulability analysis of a synchronization protocol based on replenishment-bounded overrun for compositional real-time systems 基于补货有界超限的组合实时系统同步协议全局可调度性分析

7th IEEE International Symposium on Industrial Embedded Systems (SIES'12) Pub Date : 2012-06-20 DOI: 10.1109/SIES.2012.6356568

S. Cranen, R. J. Bril

{"title":"Global schedulability analysis of a synchronization protocol based on replenishment-bounded overrun for compositional real-time systems","authors":"S. Cranen, R. J. Bril","doi":"10.1109/SIES.2012.6356568","DOIUrl":"https://doi.org/10.1109/SIES.2012.6356568","url":null,"abstract":"Hierarchical scheduling frameworks (HSFs) provide means for composing complex real-time systems from well-defined independently developed and analyzed subsystems. To support shared logical resources requiring mutual exclusive access in two-level HSFs, overrun without payback has been proposed as a mechanism to prevent budget depletion during resource access arbitrated by the stack resource policy (SRP). The same mechanism can be applied to support scheduling techniques, such as fixed-priority scheduling with deferred preemption (FPDS), that aim at a reduction of the architecture-related preemption costs and may improve the feasibility of a system. Whereas the blocking times and overrun budgets for shared logical resources will typically be much smaller than the normal budget, these values may significantly increase for scheduling techniques such as FPDS. In this paper, we therefor consider replenishment-bounded overrun, i.e. the overrun ends upon a replenishment, because the normal budget becomes available again, which allows for larger overrun budgets. We show that the global schedulability analysis for this special kind of overrun has a number of anomalies: (i) the usual theorem for critical instant does not hold, (ii) maximal blocking does not necessarily lead to a maximal response time, and (iii) it is not sufficient to analyse a fixed amount of time (say, a number of hyperperiods). We present analysis for two subsystems.","PeriodicalId":219258,"journal":{"name":"7th IEEE International Symposium on Industrial Embedded Systems (SIES'12)","volume":"379 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116578551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0