Combining instruction set simulation and WCET analysis for embedded software performance estimation

Abstract

Simulation-based approaches to evaluate the functional and non-functional properties of embedded software are in widespread industrial use for design space exploration and virtual prototyping. As simulation performance is usually the main concern for these tools, they often lack an accurate timing model of the underlying processor. On the other hand, tools aimed at the worst-case execution time (WCET) analysis of embedded software contain accurate models for the timing behavior of embedded processors. Yet, these accurate processor models are only used to determine the worst-case path through the analyzed program. This paper proposes the combination of existing tools from both domains. The combination of an a priori analysis of machine code with a dynamic selection of basic block timing estimates during the execution of the program in a high-speed instruction set simulator (ISS) reduces the simulation overhead for cycle-accurate timing estimation. By keeping track of the execution history during execution of the analyzed software, the full accuracy of the offline performance model can be used without introducing pessimism to the simulation-based performance estimates. As most of the timing estimation is done before the simulation, only a slight decrease in simulation performance of the high-speed ISS can be expected.