{"title":"Performance Aspects of PROFINET IO","authors":"H. Kleines, S. Detert, M. Drochner, F. Suxdorf","doi":"10.1109/RTC.2007.4382777","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382777","url":null,"abstract":"Recently, the complex PROFINET CBA (component based automation) has been supplemented by the simplified PROFINET IO standard. PROFINET CBA defines a vendor-independent engineering model covering plant-wide automation and uses a component/container approach. Contrary to this, PROFINET IO aims at decentral periphery scenarios. Analogous to PROFIBUS DP it is based on a modular device model. Functionally, PROFINET IO can be considered as an Ethernet-based fieldbus. It is expected that PROFINET IO will play a major role on the PLC market since it is a possible replacement for PROFIBUS DP. The paper introduces the PROFINET technology and discusses performance aspects. Measurement results are presented.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117226526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Lacasta, E. Cochran, K. Honscheid, G. Llosá, A. Studen
{"title":"DAQ++: A C++ Data Acquisition Software Framework","authors":"C. Lacasta, E. Cochran, K. Honscheid, G. Llosá, A. Studen","doi":"10.1109/RTC.2007.4382786","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382786","url":null,"abstract":"This paper describes DAQ++, a C++ based framework for developing data acquisition software. The design of DAQ++ is fully object oriented (OO) and provides a hierarchy of objects that allow a full control of the acquisition system and, also, on-line monitoring and storage of data. Being an OO system, it is easy to extend the DAQ system over several machines using a CORBA based architecture which is also provided by DAQ++. Finally, the paper describes a DAQ software system, VMEDAQ, developed with DAQ++ for the data acquisition in the CIMA collaboration. It provides a GUI which controls the objects based on the DAQ++ hierarchy. VMEDAQ has been built in a modular way which allows to add dynamically user defined data producers or DAQ++ Modules and, even, data receivers or RunManagers that allow to define different data acquisition modes like, for instance, parameter scanning.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116404646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Catastini, F. Crescioli, M. Dell'Orso, P. Giannetti, F. Palla
{"title":"The CDF Associative Memory for a Level-1 Tracking System at CMS","authors":"P. Catastini, F. Crescioli, M. Dell'Orso, P. Giannetti, F. Palla","doi":"10.1109/RTC.2007.4382818","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382818","url":null,"abstract":"The CDF associative-memory device, AM, proven technology developed for the Silicon-Vertex-Trigger at the CDF experiment, is one of the proposed solutions at CMS for track reconstruction at Level-1 in the Super-LHC very high-luminosity conditions (100 proton-proton collisions every 12.5 ns, at 1035 cm-2 sec-1). This luminosity requires a drastic revision of the existing trigger strategies. SVT is the most powerful tracker operated at a hadron collider so far. It is a unique example of on-line b-quark selection in HEP. The most CPU intensive part of the pattern recognition is solved by the AM device, where pre-calculated candidate tracks are stored. We propose the extension of the AM use to a pixel based Level-1 trigger for the super-LHC. The trigger is based on fast track reconstruction using the full pixel granularity. The trigger will implement the current CMS High Level Trigger functionality in a novel detector concept. A possible layout is discussed and performances are shown.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114075030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A framework for constructing adaptive and reconfigurable systems","authors":"P.-E. Poirot, J. Nogiec, Shangping Ren","doi":"10.1109/RTC.2007.4382751","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382751","url":null,"abstract":"This paper presents a software approach to augmenting existing real-time systems with self-adaptation capabilities. In this approach, based on the control loop paradigm commonly used in industrial control, self-adaptation is decomposed into observing system events, inferring necessary changes based on a functional model, and activating appropriate adaptation procedures. The solution adopts an architectural decomposition that emphasizes independence and separation of concerns. It encapsulates observation, analysis and correction into separate modules to allow for easier customization of the adaptive behaviors and flexibility in selecting implementation technologies.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130294220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"System Electronics and DAQ for the Silicon Vertex Detector Upgrade for PHENIX","authors":"E. Mannel","doi":"10.1109/RTC.2007.4382843","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382843","url":null,"abstract":"The PHENIX experiment at RHIC will be upgraded with a silicon vertex detector (VTX). The VTX is comprised of 4 barrels of silicon detectors. The inner two barrels will be implemented with pixel detectors read out using the ALICE1LHCb readout chip. The pixel detectors and readout chips are mounted on a high density interconnect (PIXEL bus) allowing data to be read out at 10 MHz. The outer two barrels will be implemented with a novel stripixel sensor designed by the Brookhaven National Laboratory Instrumentation Division. Each stripixel sensor will be instrumented with 12 SVX4 readout chips and controlled by a custom ASIC designed at Oak Ridge National Laboratory allowing for high speed read out. We will report of the design and status of the read out and Data Acquisition system for PHENIX VTX detector.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126852638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Bhasin, D. Evans, G. Jones, P. Jovanović, A. Jusko, L. Kralik, M. Krivda, C. Lazzeroni, R. Lietava, L. Šándor, J. Urban, O. Baillie
{"title":"Implementation of the ALICE Trigger System","authors":"A. Bhasin, D. Evans, G. Jones, P. Jovanović, A. Jusko, L. Kralik, M. Krivda, C. Lazzeroni, R. Lietava, L. Šándor, J. Urban, O. Baillie","doi":"10.1109/RTC.2007.4382861","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382861","url":null,"abstract":"The ALICE trigger system consists of the Central Trigger Processor (CTP) and 24 Local Trigger Units (LTU) that act as a uniform interface to sub-detector front-end electronics. The CTP generates three levels of hierarchical hardware triggers - L0, L1 and L2. At any time, the 24 sub-detectors of the ALICE experiment are dynamically partitioned into up to 6 independent clusters. Trigger selection includes the past-future protection a fully programmable hardware mechanism of controlling the event pile-up. The system contains a number of options that enhance the testability: the SnapShot memories both emulate logic inputs and monitor the logic operation - they enable on-line and in situ detection of system malfunction; more than 1200 signal counters, with simple on-line access, monitor the system performance and check the consistency; the ScopeProbe option enables a direct oscilloscope access to the system inputs, outputs and relevant internal signals. Some of the \"common\" CTP functions - down-scaling of trigger classes, synchronization of trigger inputs, etc. - have been realized in a way that is economical on logic resources and offers performance benefits. The implementation of those options using the FPGAs is the main topic of the presentation.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127012000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Acernese, P. Amico, M. Alshourbagy, F. Antonucci, S. Aoudia, P. Astone, S. Avino, D. Babusci, G. Ballardin, F. Barone, L. Barsotti, M. Barsuglia, T. Bauer, F. Beauville, S. Bigotta, S. Birindelli, M. Bizouard, C. Boccara, F. Bondu, L. Bosi, C. Bradaschia, S. Braccini, F. J. V. D. Brand, A. Brillet, V. Brisson, D. Buskulic, E. Calloni, E. Campagna, F. Carbognani, F. Cavalier, R. Cavalieri, G. Cella, E. Cesarini, É. Chassande-Mottin, N. Christensen, C. Corda, A. Corsi, F. Cottone, A. Clapson, F. Cleva, J. Coulon, E. Cuoco, A. Dari, V. Dattilo, M. Davier, M. Prete, R. Rosa, L. Fiore, A. Virgilio, B. Dujardin, A. Eleuteri, M. Evans, I. Ferrante, F. Fidecaro, I. Fiori, R. Flaminio, J. Fournier, S. Frasca, F. Frasconi, L. Gammaitoni, F. Garufi, E. Génin, A. Gennai, A. Giazotto, G. Giordano, L. Giordano, R. Gouaty, D. Grosjean, G. Guidi, S. Hamdani, S. Hebri, H. Heitmann, P. Hello, D. Huet, S. Karkar, S. Kreckelbergh, P. Penna, M. Laval, N. Leroy, N. Letendre, B. Lopez, M. Lorenzini, V. Loriette, G. Losurdo,
{"title":"Data Acquisition System of the Virgo Gravitational Waves Interferometric Detector","authors":"F. Acernese, P. Amico, M. Alshourbagy, F. Antonucci, S. Aoudia, P. Astone, S. Avino, D. Babusci, G. Ballardin, F. Barone, L. Barsotti, M. Barsuglia, T. Bauer, F. Beauville, S. Bigotta, S. Birindelli, M. Bizouard, C. Boccara, F. Bondu, L. Bosi, C. Bradaschia, S. Braccini, F. J. V. D. Brand, A. Brillet, V. Brisson, D. Buskulic, E. Calloni, E. Campagna, F. Carbognani, F. Cavalier, R. Cavalieri, G. Cella, E. Cesarini, É. Chassande-Mottin, N. Christensen, C. Corda, A. Corsi, F. Cottone, A. Clapson, F. Cleva, J. Coulon, E. Cuoco, A. Dari, V. Dattilo, M. Davier, M. Prete, R. Rosa, L. Fiore, A. Virgilio, B. Dujardin, A. Eleuteri, M. Evans, I. Ferrante, F. Fidecaro, I. Fiori, R. Flaminio, J. Fournier, S. Frasca, F. Frasconi, L. Gammaitoni, F. Garufi, E. Génin, A. Gennai, A. Giazotto, G. Giordano, L. Giordano, R. Gouaty, D. Grosjean, G. Guidi, S. Hamdani, S. Hebri, H. Heitmann, P. Hello, D. Huet, S. Karkar, S. Kreckelbergh, P. Penna, M. Laval, N. Leroy, N. Letendre, B. Lopez, M. Lorenzini, V. Loriette, G. Losurdo, ","doi":"10.1109/RTC.2007.4382842","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382842","url":null,"abstract":"Virgo is an experiment aiming at the detection of gravitational waves emitted by astrophysical sources. Its detector, based on a 3 km arms interferometer, is a complex setup which requires several digital control loops running up to 10 kHz, an accurate and reliable central timing system and an efficient data acquisition, all of them being distributed over 3 km. We overview here the main hardware and software components developed for the data acquisition system (DAQ) and its current architecture. Then, we briefly discuss its connections with interferometer's controls, especially through the automation of the interferometer's startup procedure. Then, we describe the tools used to monitor the DAQ and the performances we measured with them. Finally, are described also the tools developed for the online detector monitoring, mandatory complement of the DAQ for the commissioning of the virgo detector.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123125842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Digital Frequency Domain Multiplexer for mm-Wavelength Telescopes","authors":"M. Dobbs, E. Bissonnette, H. Spieler","doi":"10.1109/RTC.2007.4382760","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382760","url":null,"abstract":"An FPGA based digital signal processing (DSP) system for biasing and reading out multiplexed bolometric detectors for mm-wavelength telescopes is presented. This readout system is being deployed for balloon-borne and ground based cosmology experiments with the primary goal of measuring the signature of inflation with the cosmic microwave background radiation. The system consists of analog superconducting electronics running at 250 mK and 4 K, coupled to digital room temperature backend electronics described here. The digital electronics perform the real time functionality with DSP algorithms implemented in firmware. A soft embedded processor provides all of the slow housekeeping control and communications. Each board in the system synthesizes multi-frequency combs of 8 to 32 carriers in the MHz band to bias the detectors. After the carriers have been modulated with the sky-signal by the detectors, the same boards digitize the comb directly. The carriers are mixed down to base-band and low pass filtered. The signal bandwidth of 0.050 Hz -100 Hz places extreme requirements on stability and requires powerful filtering techniques to recover the sky-signal from the MHz carriers.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"71 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120995913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Angstadt, J. Estrada, H. Diehl, B. Flaugher, M. Johnson
{"title":"Microsecond Delays on Non-Real Time Operating Systems","authors":"R. Angstadt, J. Estrada, H. Diehl, B. Flaugher, M. Johnson","doi":"10.1109/RTC.2007.4382803","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382803","url":null,"abstract":"We have developed microsecond timing and profiling software that runs on standard Windows and Linux based operating systems. This software is orders of magnitudes better than most of the standard native functions in wide use. Our software libraries calibrate RDTSC in microseconds or seconds to provide two different types of delays: a \"guaranteed minimum\" and a precision \"long delay\", which releases to the kernel. Both return profiling information of the actual delay.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132026257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Kammerling, A. Ackens, H. Loevenich, A. Borga, P. Wustner, G. Kemmerling, W. Erven, K. Zwoll, H. Kleines, M. Drochner
{"title":"FPGA Configuration by TCP/IP and Ethernet","authors":"P. Kammerling, A. Ackens, H. Loevenich, A. Borga, P. Wustner, G. Kemmerling, W. Erven, K. Zwoll, H. Kleines, M. Drochner","doi":"10.1109/RTC.2007.4382790","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382790","url":null,"abstract":"A RAM based FPGA can be configured with a bootimage from a local proprietary flash prom, by a JTAG adapter hooked to a local PC interface or any another component, which copes with one of the FPGA configuration protocols. The development of the FPGA code as well as updates of the bootimage can be done by a JTAG adapter. On the basis of a PCB developed in the ZEL we show a first step towards an embedded JTAG adapter for TCP/IP-Ethernet.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126877214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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