{"title":"An Operation-Server Based Data Acquisition System Architecture","authors":"C. Robson, Samuel Silverstein, Christian Bohm","doi":"10.1109/RTC.2007.4382788","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382788","url":null,"abstract":"Developments in networked embedded system technologies and programmable logic are making it possible to design new, highly flexible data acquisition system (DAQ) architectures. We present a networked DAQ system architecture where the software resources required by the DAQ units are acquired from a server dynamically, to be stored and executed in local memory. When the DAQ unit needs to call an operation not contained in its memory, the new operation is requested from the server, while resources occupied by operations that have not been used recently are released to make space for it. In this way it is possible to reduce the resource use of the embedded DAQ unit to only what is necessary for efficient operation in its major modes. Since new code is easily distributed to the DAQ units from the server, system upgrades are also simplified.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124408555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Shared Dataspace Communication Framework for Data Acquisition System","authors":"Y. Nagasaka, H. Motoyama","doi":"10.1109/RTC.2007.4382854","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382854","url":null,"abstract":"A shared dataspace communication framework for data acquisition system has been developed. The framework helps us to develop the data acquisition system easily and efficiently. It has been developed on the concept of shared dataspace with using a repository. The repository has data and their index keys, and it can be accessed with easy communication commands,PUT,GET,DELETE,NOTIFY and LINK, by the component. The data are managed by the index key in the repository. The component can access the data in the repository by specifying the key related to the data. The new communication command,NOTIFY and LINK, were also introduced in this framework for a management of the data in the repository. The data acquisition system developer can develop the system easily and efficiently with the shared dataspace communication framework.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125036402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Fortunato, A. Batista, J. Sousa, H. Femandes, C. Varandas
{"title":"Event and pulse node hardware for nuclear fusion experiments","authors":"J. Fortunato, A. Batista, J. Sousa, H. Femandes, C. Varandas","doi":"10.1109/RTC.2007.4382796","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382796","url":null,"abstract":"This article presents an event and pulse node hardware module (EPN) being developed for use in control and data acquisition (CODAC) in current and upcoming long discharges nuclear fusion experiments. Its purpose is to allow real time event management and trigger distribution. The use of a mixture of digital signal processing and field programmable gate arrays, with fiber optic channels for event broadcast between CODAC nodes, and short length paths between the EPN and CODAC hardware, allows an effective and low latency communication path. This hardware will be integrated in the ISTTOK CODAC to allow long AC plasma discharges.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123991348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Valero, J. Abdallah, V. Castillo, C. Cuenca, A. Ferrer, E. Fullana, V. González, E. Higón, J. Poveda, A. Ruiz-Martinez, B. Salvachua, E. Sanchis, C. Solans, J. Torres
{"title":"TileCal Optical Multiplexer Board 9U prototype","authors":"A. Valero, J. Abdallah, V. Castillo, C. Cuenca, A. Ferrer, E. Fullana, V. González, E. Higón, J. Poveda, A. Ruiz-Martinez, B. Salvachua, E. Sanchis, C. Solans, J. Torres","doi":"10.1109/RTC.2007.4382755","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382755","url":null,"abstract":"This paper presents the architecture and the status of the optical multiplexer board (OMB) for the ATLAS/LHC Tile hadronic calorimeter (TileCal). This board will analyze the front-end data CRC to prevent bit and burst errors produced by radiation. Besides, due to its position within the data acquisition chain it will be used to emulate front-end data for tests. The first two prototypes of the final OMB 9U version have been produced at CERN. Detailed design issues and manufacture features of these prototypes are described. These prototypes are being validated whereas some firmware developments are being implemented in the programmable devices of the board. Functional descriptions of the board on its two main operation modes as CRC checking and data ROD injector are explained as well as other functionalities. Finally, the schedule for next year when the production of the OMB will be take place is also presented.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134153680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Penno, T. Grevsmuhl, H. Leich, A. Kretzschmann, W. Kohler, B. Petrosyan, G. Trowitzsch, R. Wenndorff
{"title":"A Configurable Interlock System for RF-Stations at XFEL","authors":"M. Penno, T. Grevsmuhl, H. Leich, A. Kretzschmann, W. Kohler, B. Petrosyan, G. Trowitzsch, R. Wenndorff","doi":"10.1109/RTC.2007.4382740","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382740","url":null,"abstract":"The main task of the interlock system is to prevent any damage to the cost expensive components of the RF station. The implementation of the interlock should guarantee a maximum of uninterrupted time of operation which includes the implementation of self diagnostic and repair strategies on module basis. Additional tasks include collection and temporary storage of status information of individual channels; transfer of this information to a higher level control system, but also the enactment of slow control functions. The interlock implementation is based on a 4U 19\"-Crate which houses a controller and different slave modules which implement the interface to the components of the RF station. A dedicated, user defined backplane connects the controller to all slave modules. The Controller incorporates a 32-bit RISC NIOS-II processor inside a Cyclone-II FPGA device from ALTERA. The program running on this processor performs all necessary control and monitoring functions to all slave modules in the crate, but not the interlock function itself. The interlock function is implemented as hardwired logic and keeps working, even if the processor stops or the program hangs up. The software performs a system-test on power-up, to test the hardware functionality and the crate configuration. On success, the interlock hardware gets configured for operation and the crate is put into the working state. After initialization higher level applications get loaded. This covers the communication interface to the control system and a diagnostic interface, which is used during installation and trouble shooting. For this purpose, LabVIEW tools are used to present information. In addition, a HTTP server on the interlock controller provides the possibility to change configuration and view actual status information. It also implements tools which allow to reconfigure the whole FPGA design or to upload a new software version via Ethernet.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133644256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fast waveform digitization with the DRS chip","authors":"S. Ritt","doi":"10.1109/RTC.2007.4382753","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382753","url":null,"abstract":"The DRS chip was developed recently at PSI, Switzerland, using a 0.25 mum radiation hard CMOS technology. It implements a series of switched capacitor arrays (SCA), which allow the digitization of signals at speeds up to 5 GHz, at a power consumption and fabrication cost orders of magnitude lower than conventional flash ADCs. This allows a new generation of experiments with superior pile-up rejection and pulse shape discrimination, while simultaneously eliminating the need for traditional ADCs and TDCs. This paper explains the operating principle of the DRS chip and describes the deployment in the MEG experiment using 3000 channels in the MIDAS DAQ framework. Real time aspects of the data acquisition are covered and solutions are shown how to overcome the 880 MB/s raw data rate of the MEG experiment.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131333326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using Feedback to Control Deadtime in the CDF Trigger System","authors":"D. Torretta","doi":"10.1109/RTC.2007.4382852","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382852","url":null,"abstract":"The CDF experiment uses a three-level trigger system to select events produced during pp macr collisions. As the luminosity of the Tevatron accelerator falls by a factor of four over a 24 hour period, trigger selections are adjusted automatically in order to make full use of the data processing bandwidth. The selections are made to maximize high purity triggers and keep the deadtime as low as possible at any given luminosity thoughout the entire course of a run. We describe the algorithms used to obtain these goals and how the changing conditions are accounted for in the analysis of the data.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115795139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Improvement of TLSF Algorithm","authors":"X. Sun, J. Wang, Xiao Chen","doi":"10.1109/RTC.2007.4382781","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382781","url":null,"abstract":"Memory management has become an important part in developing real-time and embedded applications. The conventional dynamic storage allocation (DSA) algorithms have been considered inappropriate for real-time applications due to the unbounded response time and fragmentation problem. There are some new allocators designed to meet the requirements nowadays. Two-Level Segregated Fit memory allocator (TLSF) was proposed and widely used in the Real-Time Operating Systems (RTOS) like RTLinux. It has a bounded response time and quite good performance. However, there are still some problems with this algorithm and it could be improved. Here we discuss some improvements of the TLSF algorithm. Experiments show it has low fragmentation and faster response time.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116937555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Sukhanov, I. Sukhanov, Suhyeon Kim, A. Shutov, S. Bazylev
{"title":"Online Monitoring and Remote FPGA Configuration Using JTAG Over Ethernet","authors":"A. Sukhanov, I. Sukhanov, Suhyeon Kim, A. Shutov, S. Bazylev","doi":"10.1109/RTC.2007.4382778","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382778","url":null,"abstract":"JTAG interface of FPGA devices can be used as a low-footprint general-purpose communication port, providing powerful and flexible test and debug capability to a design. A JTAG micro-controller based on off-the-shelf components and free software is designed and tested. It provides fast configuration of long FPGA chains over ethernet at 500 kgates/s, it supports most of the common file formats. It can be used for slow control monitoring (100 kb/s) and moderate data taking (2 MByte/s).","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125756884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Framework of BESIII Event Filter","authors":"Yingjie Liu, K. Zhu, Jingwei Zhao","doi":"10.1109/RTC.2007.4382815","DOIUrl":"https://doi.org/10.1109/RTC.2007.4382815","url":null,"abstract":"The BES III (Beijing Spectrometer III) is a general purpose detector at BEPC II (Beijing Electron Positron Collider II) currently under construction in Beijing. Based on the framework of Atlas TDAQ (trigger and data acquisition) software, the BESIII event filter software consists of the EFD (event filter dataflow) component and the PT (processing task) component which invokes the offline event selection procedure to analyze the events and make decisions. The primary function of event filter is to fetch full events from the event builder, analyze them with physics event selection algorithms, and send the accepted events to the event storage sub-system. In particular, in order to increase system reliability, two methods are introduced: (1) timeout PT will be killed by the corresponding EFD. (2) Standby lines will be automatically opened when normal lines cannot satisfy the rated data flow. This paper focuses on the framework architecture, system reliability and stability of the BES III event filter software.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128703860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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