{"title":"A carrier-based discontinuous space vector modulation for three-level NPC inverter","authors":"Chengzhu Piao, J. Hung","doi":"10.1109/IWIPP.2015.7295982","DOIUrl":"https://doi.org/10.1109/IWIPP.2015.7295982","url":null,"abstract":"This paper presents carrier-based discontinuous space vector pulse width modulation (DSVPWM) method for three-level three-phase neutral point clamped (NPC) voltage source inverter (VSI). Based on the relationship between space vector pulse width modulation (SVPWM) and carrier based modulation, a simplified DSVPWM method for three-phase inverter is introduced by skillfully arranging two zero voltage vectors. In this method, the conventional space vector modulator with equal division of zero voltage vector time is modified to generate different discontinuous modulating waves. The switching sequences for six basic types of discontinuous PWM are studied. It includes DSVPWMmax, DSVPWMmin, DSVPWM0, DSVPWM1, DSVPWM2, and DSVPWM3. According to the carrier-based PWM, simplified SVPWM, and traditional discontinuous PWM strategies, the DSVPWM strategies called as DSVPWMx, including six basic types of DSVPWM and eight novel types of DSVPWM, are proposed and studied. By this method, switching losses of inverter are optimized and life expectancy of inverter can be increased using a suitable discontinuous modulation technique. The proposed method is theoretically analyzed, and verified by simulation results.","PeriodicalId":214539,"journal":{"name":"2015 IEEE International Workshop on Integrated Power Packaging (IWIPP)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122978160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermal management of lateral GaN power devices","authors":"C. Yu, E. Labouré, C. Buttay","doi":"10.1109/IWIPP.2015.7295973","DOIUrl":"https://doi.org/10.1109/IWIPP.2015.7295973","url":null,"abstract":"This article investigates several thermal management techniques for GaN transistors with a Wafer-Level Packaging (WLP): advanced techniques are used to mount them on Direct-Bonded Copper (DBC) ceramic substrates, with the heat removed either through the topside of the die (as recommended by the manufacturer), or through the backside. The thermal resistance of the assembly is measured in the different configurations, for different die thicknesses. The paper describes the manufacturing process and the thermal simulation and experimental results will be shown.","PeriodicalId":214539,"journal":{"name":"2015 IEEE International Workshop on Integrated Power Packaging (IWIPP)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130434257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Murthy-Bellur, Elias Ayana, S. Kunin, B. Palmer, S. Varigonda
{"title":"WBG inverter for commercial power generation and vehicle electrification","authors":"D. Murthy-Bellur, Elias Ayana, S. Kunin, B. Palmer, S. Varigonda","doi":"10.1109/IWIPP.2015.7295972","DOIUrl":"https://doi.org/10.1109/IWIPP.2015.7295972","url":null,"abstract":"In recent years, commercially available wide bandgap (WBG) devices and modules have sparked significant interest among several industries to develop power electronics using WBG technology. The commercial viability and benefits of developing such WBG power electronics are visibly increasing. However, there exists a great deal of information disconnect between the WBG semiconductor manufacturers and the end users. Reducing this gap requires immediate attention from all entities in the supply chain of power electronics industry to fully extract the capabilities of WBG technology. This paper introduces the use of power electronics in power generation and vehicle electrification applications. Using examples, potential use of WBG semiconductors in these applications are discussed. Requirements of power semiconductor modules for power electronics applied to power generation and medium- to heavy-duty vehicles are also presented.","PeriodicalId":214539,"journal":{"name":"2015 IEEE International Workshop on Integrated Power Packaging (IWIPP)","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132907604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a reduced form factor passive heat sink for high power applications","authors":"S. Seal, M. Glover, H. Mantooth","doi":"10.1109/IWIPP.2015.7295974","DOIUrl":"https://doi.org/10.1109/IWIPP.2015.7295974","url":null,"abstract":"This paper presents the design of a reduced form factor passive heat sink that can be used to sink heat effectively in modules operating in the 2-5 kW power range. Fin- or pin-fin-type passive heat sinks that are commercially available today are incapable of achieving comparable heat sinking performance with comparable volume. This paper focuses on the development of a bonded fin heat sink, showing how the heat sinking capacity changes with parameters such as fin density and fin thickness. Alternative high-performance materials for the fins were also probed. Choosing lighter materials with high thermal conductivity showed an increase in both power density and specific power as compared to using copper as the heat sink fin material.","PeriodicalId":214539,"journal":{"name":"2015 IEEE International Workshop on Integrated Power Packaging (IWIPP)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130960942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power electronics packaging challenges for future warship applications","authors":"R. Cuzner","doi":"10.1109/IWIPP.2015.7295965","DOIUrl":"https://doi.org/10.1109/IWIPP.2015.7295965","url":null,"abstract":"Power conversion and solid state protection technologies are critical enablers to the accomplishment of the Navy's vision for shipboard Next Generation Integrated Power Systems but for most commercial offerings of this equipment the simultaneous achievements of high power density with electromagnetic and thermal compatibility and high reliability are prohibitive cost drivers. The increasing availability of wide bandgap power semiconductors provides the opportunity for the development of power electronic systems with a smaller footprint, higher efficiency and lower demands for external thermal management - enabling more widespread introduction of power electronic systems into the shipboard environment with lower system integration costs. However, the shipboard environment poses challenging competing requirements that cannot be ignored. The purpose of this paper is to highlight the future packaging challenges in three areas: modularity, increased module functionality and retrofit. These challenges are illustrated by three specific examples: medium voltage solid state transformer, medium voltage dc solid state circuit breaker and low voltage variable speed drive.","PeriodicalId":214539,"journal":{"name":"2015 IEEE International Workshop on Integrated Power Packaging (IWIPP)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129891569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"6.5 kV Si/SiC hybrid power module: An ideal next step?","authors":"A. Huang, Xiaoqing Song, Liqi Zhang","doi":"10.1109/IWIPP.2015.7295979","DOIUrl":"https://doi.org/10.1109/IWIPP.2015.7295979","url":null,"abstract":"Silicon carbide (SiC) power switches such as JFET or MOSFET have demonstrated their superior advantages over silicon (Si) power devices such as IGBT, especially in terms of significantly reduced switching losses. A major issue facing large scale adoption of SiC power devices is still the much higher cost. This paper proposes that Si/SiC hybrid power module (HPM) should be a natural next step moving forward for high voltage applications to address the cost issue. In the proposed Si/SiC HPM, a SiC JFET is connected in parallel with Si IGBT to combine the advantages of both IGBT and JFET. A 6.5 kV HPM is developed based on Si IGBT and SiC JFET as an example to demonstrate its superior cost/performance. The switching loss can be reduced by more than 70% at a cost of about 70% higher compared to Si IGBT. This work is especially essential for high voltage applications such as medium voltage motor drive, FACTS and HVDC systems.","PeriodicalId":214539,"journal":{"name":"2015 IEEE International Workshop on Integrated Power Packaging (IWIPP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129190134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ernie Parker, B. Narveson, A. Alderman, Louis Burgyan
{"title":"Embedding active and passive components in PCBs and inorganic substrates for power electronics","authors":"Ernie Parker, B. Narveson, A. Alderman, Louis Burgyan","doi":"10.1109/IWIPP.2015.7295990","DOIUrl":"https://doi.org/10.1109/IWIPP.2015.7295990","url":null,"abstract":"The Packaging Committee of the Power Sources Manufacturers Association (PSMA) organized and sponsored a special project to study how innovations in 3D packaging either were currently or are projected to be leveraged by the power electronics industry. Phase 1 of this special project resulted in a Technology Report titled “3D Power Packaging” [1] that was prepared under contract by Tyndall Institute of Cork, Ireland and published March 2014. Phase 2 of the special project continued to examine 3D power packaging but with a focus on embedded substrate technologies; it was prepared under contract LTEC Corporation with subcontract to Anagenesis, Inc. and Fraunhofer-Institure and was published March 2015 [2]. The phase 2 report covers a spectrum from active and passive component technologies for embedding, die attach materials and processes, thermal management, and additive manufacturing; however the heart of the report is a chapter on technologies for embedding in PCBs and inorganic substrates. This paper provides an overview of the findings from that report regarding technologies that are currently in production and those forecast to be viable for volume production in the near future.","PeriodicalId":214539,"journal":{"name":"2015 IEEE International Workshop on Integrated Power Packaging (IWIPP)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117329041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Parasitic extraction procedure for silicon carbide power modules","authors":"A. Lemmon, R. Graves","doi":"10.1109/IWIPP.2015.7295986","DOIUrl":"https://doi.org/10.1109/IWIPP.2015.7295986","url":null,"abstract":"Parasitic impedances play a significant role in determining the achievable performance of power electronics applications based on wide band-gap semiconductors. Unlike applications based on traditional devices, this new class of applications has spectral content in the \"near-RF\" domain, which can reveal anomalous system behavior by exciting resonances in these parasitic impedances. To understand and mitigate this behavior, it is important that application designers have some means for estimating the interconnect impedances within multi-chip power modules (MCPM's). This paper proposes a straightforward methodology for extracting estimates of parasitic impedances within the MCPM structure, without a-priori knowledge of the module geometry or interconnection details. The practical utility of the proposed approach is demonstrated through the execution of a case study involving a commercially-available MCPM; and the resulting impedance estimates are empirically validated through switching experiments.","PeriodicalId":214539,"journal":{"name":"2015 IEEE International Workshop on Integrated Power Packaging (IWIPP)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123020040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Chip-level and package-level thermal constraints in power semiconductor switch modules","authors":"K. Shenai","doi":"10.1109/IWIPP.2015.7295983","DOIUrl":"https://doi.org/10.1109/IWIPP.2015.7295983","url":null,"abstract":"A simple model for heat generation and heat spreading, and temperature rise of the active region of a power semiconductor switch is presented by properly accounting for semiconductor and package thermal and heat capacity parameters. The model is used to estimate the effect of finite substrate thickness in silicon and wide bandgap (WBG) power switching devices on junction temperature rise. Whereas 4H-SiC power devices show superior thermal performance compared to either GaN or silicon power devices, calculations suggest the need to thin down the current state-of-the-art 4H-SiC substrates by at least a factor of two, and the need to increase thermal conductivity of GaN substrates. The model is also used to estimate the power-handling capability of power switch modules, and the experimental data is shown to be in good agreement with the theoretical model for 1700V/25A 4H-SiC JBS power diodes.","PeriodicalId":214539,"journal":{"name":"2015 IEEE International Workshop on Integrated Power Packaging (IWIPP)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127423727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zheyu Zhang, Zhiqiang Wang, Fred Wang, L. Tolbert, B. Blalock
{"title":"Reliability-oriented design of gate driver for SiC devices in voltage source converter","authors":"Zheyu Zhang, Zhiqiang Wang, Fred Wang, L. Tolbert, B. Blalock","doi":"10.1109/IWIPP.2015.7295968","DOIUrl":"https://doi.org/10.1109/IWIPP.2015.7295968","url":null,"abstract":"High reliability of semiconductor power devices is one of the key design objectives for power conversion systems. Fast switching SiC devices are susceptible to cross-talk, and these devices also have limited over-current capability. Both of these issues significantly threaten the reliable operation of SiC-based voltage source converters. This paper proposes two gate assist circuits capable of suppressing cross-talk and preventing shoot-through faults to promote the reliable use of SiC devices within a voltage source converter. Experimental results and detailed analysis are presented to verify the feasibility of the proposed approach.","PeriodicalId":214539,"journal":{"name":"2015 IEEE International Workshop on Integrated Power Packaging (IWIPP)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124095754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}