Proceedings 1997 27th International Symposium on Multiple- Valued Logic最新文献_第2页

Circuit design from Kronecker Galois field decision diagrams for multiple-valued functions 多值函数的克罗内克伽罗瓦场决策图电路设计

Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601413

R. Stankovic, R. Drechsler

引用次数: 39

Multiple-valued programmable logic arrays with universal literals 具有通用文字的多值可编程逻辑阵列

Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601391

T. Utsumi, N. Kamiura, Y. Hata, K. Yamato

引用次数: 7

One-transistor-cell 4-valued universal-literal CAM for cellular logic image processing 用于单元逻辑图像处理的单晶体管单元4值通用文字CAM

Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601393

T. Hanyu, M. Arakaki, M. Kameyama

引用次数: 3

Finding composition trees for multiple-valued functions 寻找多值函数的组合树

Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601368

E. Dubrova, J. Muzio, B. Stengel

引用次数: 13

Fourier decision diagrams on finite non-Abelian groups with preprocessing 有限非阿贝尔群的傅里叶决策图及其预处理

Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601415

R. Stankovic

引用次数: 13

Set-valued functions and regularity 集值函数与正则性

Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601379

N. Takagi, Y. Nakamura, K. Nakashima

引用次数: 7

Family of complex Hadamard transforms: relationship with other transforms and complex composite spectra 复哈达玛变换族:与其它变换和复复合谱的关系

Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601386

S. Rahardja, B. Falkowski

{"title":"Family of complex Hadamard transforms: relationship with other transforms and complex composite spectra","authors":"S. Rahardja, B. Falkowski","doi":"10.1109/ISMVL.1997.601386","DOIUrl":"https://doi.org/10.1109/ISMVL.1997.601386","url":null,"abstract":"Relationship of the recently introduced family of unified complex Hadamard transforms with other transforms used in binary and multiple-valued logic design are investigated in this paper. All the complex Hadamard matrices can be generated by a common unifying formula presented here. Only half of all possible 64 unified complex Hadamard transforms have half-spectrum property. The existence of such a property for 32 transformation matrices is proven for the first time in this paper. Half-spectrum property is important as h reduces the required computer storage by half when compared to other transforms operating on complex numbers. The method is also presented to evaluate complex Hadamard spectra of AND, OR, and XOR of Boolean functions directly from the spectra of the separate Boolean functions. The results are given using a general coding scheme, and different possible codings of Boolean functions are discussed. Moreover, new definition of the convolution operation called complex convolution is derived. Different properties of such a convolution are presented. Theorem giving final formulae for composite complex Hadamard spectra of Boolean functions is stated in terms of complex convolution. By using presented methods, many of the Boolean operations in original domain can be represented much simpler in terms of their composite complex spectra.","PeriodicalId":206024,"journal":{"name":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114727817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

VLSI design of a quaternary multiplier with direct generation of partial products 一种直接生成部分产品的四元乘法器的VLSI设计

Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601392

O. Ishizuka, Akihiro Ohta, K. Tanno, Zheng Tang, D. Handoko

{"title":"VLSI design of a quaternary multiplier with direct generation of partial products","authors":"O. Ishizuka, Akihiro Ohta, K. Tanno, Zheng Tang, D. Handoko","doi":"10.1109/ISMVL.1997.601392","DOIUrl":"https://doi.org/10.1109/ISMVL.1997.601392","url":null,"abstract":"This paper presents the VLSI design of a novel quaternary multiplier with direct generation of partial products using a radix-4 redundant number system. The structure of the multiplier is so simple and regular that it is suitable for VLSI implementation. Partial products in the multiplier are generated as the corresponding value 0 to 9 and are implemented by simple CMOS current-mode circuits. To add partial products in the multiplier, we introduce a redundant multi-valued adder (RMA). The RMA can add two redundant numbers without carry propagation. The resulting numbers in the final level of additions are also redundant. We use a high speed quaternary carry-lookahead adder (QCLA) to convert a redundant number into a non-redundant number. The chip of a CMOS 4/spl times/4-digit quaternary multiplier is fabricated in cooperation with the VLSI Design and Education Center of Tokyo University, Japan. The chip and core sizes of the multiplier are 2.3/spl times/2.3 mm/sup 2/ and 1.5/spl times/1.6 mm/sup 2/, respectively with 1.5 /spl mu/m technology. The layout design of a 16/spl times/16-digit quaternary multiplier with 0.8 /spl mu/m technology is also discussed for the practical use.","PeriodicalId":206024,"journal":{"name":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132319748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Design of ternary CCD circuits referencing to current-mode CMOS circuits 参考电流型CMOS电路设计三元CCD电路

Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601399

Xunwei Wu, Massoud Pedram

引用次数: 1

Fast algorithm for minimizing Reed-Muller expansions of systems of incompletely specified MVL functions 不完全指定MVL函数系统的Reed-Muller展开式的快速最小化算法

Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601375

A. Zakrevskij, L. Zakrevski

引用次数: 3