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Proceedings 1997 27th International Symposium on Multiple- Valued Logic最新文献

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Functional decomposition of MVL functions using multi-valued decision diagrams 基于多值决策图的MVL函数分解
Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601370
C. Files, R. Drechsler, M. Perkowski
{"title":"Functional decomposition of MVL functions using multi-valued decision diagrams","authors":"C. Files, R. Drechsler, M. Perkowski","doi":"10.1109/ISMVL.1997.601370","DOIUrl":"https://doi.org/10.1109/ISMVL.1997.601370","url":null,"abstract":"In this paper, the minimization of incompletely specified multi-valued functions using functional decomposition is discussed. From the aspect of machine learning, learning samples can be implemented as minterms in multi-valued logic. The representation, can then be decomposed into smaller blocks, resulting in a reduced problem complexity. This gives induced descriptions through structuring, or feature extraction, of a learning problem. Our approach to the decomposition is based on expressing a multi-valued function (learning problem) in terms of a multi-valued decision diagram that allows the use of Don't Cares. The inclusion of Don't Cares is the emphasis for this paper since multi-valued benchmarks are characterized as having many Don't Cares.","PeriodicalId":206024,"journal":{"name":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129259943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Fault simulation in sequential multi-valued logic networks 时序多值逻辑网络的故障仿真
Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601389
R. Drechsler, Martin Keim, B. Becker
{"title":"Fault simulation in sequential multi-valued logic networks","authors":"R. Drechsler, Martin Keim, B. Becker","doi":"10.1109/ISMVL.1997.601389","DOIUrl":"https://doi.org/10.1109/ISMVL.1997.601389","url":null,"abstract":"In this paper we present a fault simulator for Sequential Multi-Valued Logic Networks (SMVLN). With this tool we investigate their random pattern testability (RPT). We discuss a unified approach for fault models in SMVLNs and show that it is possible to describe all static fault models with a global formalism. A large set of experimental results is given that demonstrates the efficiency of our approach. For the first time fault coverages for the Stuck-At Fault Model (SAFM) and Skew Fault Model (SKFM) for large sequential circuits are reported.","PeriodicalId":206024,"journal":{"name":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123556518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
What is many-valued logic? 什么是多值逻辑?
Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601384
J. Béziau
{"title":"What is many-valued logic?","authors":"J. Béziau","doi":"10.1109/ISMVL.1997.601384","DOIUrl":"https://doi.org/10.1109/ISMVL.1997.601384","url":null,"abstract":"Firstly we examine the definition of many-valued logic within the framework of (logical) matrix theory. Secondly we discuss the general result, challenging the existence of many-valued logic, according to which every logic may be seen as two-valued. Thirdly we analyze the principle of bivalence and show that it appears at a deeper level than one usually thinks.","PeriodicalId":206024,"journal":{"name":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116819091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 360
Test pattern generation for combinatorial multi-valued networks based on generalized D-algorithm 基于广义d算法的组合多值网络测试模式生成
Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601388
V. Shmerko, S. Yanushkevich, V. Levashenko
{"title":"Test pattern generation for combinatorial multi-valued networks based on generalized D-algorithm","authors":"V. Shmerko, S. Yanushkevich, V. Levashenko","doi":"10.1109/ISMVL.1997.601388","DOIUrl":"https://doi.org/10.1109/ISMVL.1997.601388","url":null,"abstract":"A calculus for test pattern generation for Multi-Valued Logic (MVL) networks using so-called Direct D-cubes (DD-cubes) is proposed. The concept of the DD-cubes is introduced based on Direct Logic Derivatives generated by a matrix algorithm. It provides a means to support the central stages of test generating on parallel hardware, for instance, linear systolic arrays.","PeriodicalId":206024,"journal":{"name":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127329581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A useful application of CMOS ternary logic to the realisation of asynchronous circuits CMOS三元逻辑在异步电路实现中的一个有用应用
Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601398
R. Mariani, R. Roncella, R. Saletti, P. Terreni
{"title":"A useful application of CMOS ternary logic to the realisation of asynchronous circuits","authors":"R. Mariani, R. Roncella, R. Saletti, P. Terreni","doi":"10.1109/ISMVL.1997.601398","DOIUrl":"https://doi.org/10.1109/ISMVL.1997.601398","url":null,"abstract":"This paper shows how the application of a CMOS ternary logic is useful in the realisation of delay insensitive (DI) asynchronous circuits. It is shown that fully DI asynchronous circuits are obtained with a ternary handshake protocol which employs the third logic level as idle state of the asynchronous interface. The advantages obtained are a dramatic reduction of the communication requirement and a lower power consumption as compared to other asynchronous solutions. It is then discussed how general purpose delay-insensitive circuits can be designed with ternary logic elements and finally an asynchronous sequence recognition circuit is described as an application of the approach.","PeriodicalId":206024,"journal":{"name":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114973296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Ternary decision diagrams. Survey 三元决策图。调查
Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601404
Tsutomu Sasao
{"title":"Ternary decision diagrams. Survey","authors":"Tsutomu Sasao","doi":"10.1109/ISMVL.1997.601404","DOIUrl":"https://doi.org/10.1109/ISMVL.1997.601404","url":null,"abstract":"This paper surveys seven types of TDDs: General-TDD, SOP-TDD, ESOP-TDD, AND-TDD, prime-TDD, EXOR-TDD, and Kleene-TDD. We give new definitions for SOP-TDDs and ESOP-TDDs and introduce unifying terminology. After showing some theorems on complexities, we compare the sizes of these TDDs using benchmark functions. Finally, we review important works on TDDs.","PeriodicalId":206024,"journal":{"name":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133051927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Representation of uncertain belief using interval probability 用区间概率表示不确定信念
Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601382
P. Giang
{"title":"Representation of uncertain belief using interval probability","authors":"P. Giang","doi":"10.1109/ISMVL.1997.601382","DOIUrl":"https://doi.org/10.1109/ISMVL.1997.601382","url":null,"abstract":"In this paper, uncertain belief representation by using probability is investigated. The representation equivalence between interval probability suggested by D.D. Phan (1990) and convex set of probability distribution by H. Kyburg (1990) is proved. Probabilistic closures using classical and relevant consequence relations are defined and compared. Their agreement on a non-tautological fragment is proved.","PeriodicalId":206024,"journal":{"name":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131444915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Quaternary dynamic differential logic with application to fuzzy-logic circuits 四元动态微分逻辑及其在模糊逻辑电路中的应用
Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601400
A. Herrfeld, S. Hentschke
{"title":"Quaternary dynamic differential logic with application to fuzzy-logic circuits","authors":"A. Herrfeld, S. Hentschke","doi":"10.1109/ISMVL.1997.601400","DOIUrl":"https://doi.org/10.1109/ISMVL.1997.601400","url":null,"abstract":"This paper introduces a new dynamic quaternary CMOS technique. Using only standard enhancement MOSFETs with no threshold modifications was one aim of the development. The difference between two successive logical voltages has to be greater than the threshold voltages of the MOSFETs. Thereby, a high noise margin can be reached. The paper shows dynamic circuits for connecting the quaternary circuits with binary ones. Furthermore, quaternary OR- and AND-gates are given. In connection with literal-operators, all quaternary logic functions can be realized with the technique introduced. In addition, four Fuzzy-logic circuits are shown, namely a bounded-sum and a bounded-difference circuit as well as a drastic-product and a drastic-sum circuit.","PeriodicalId":206024,"journal":{"name":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128966765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Multiple-junction surface tunnel transistors for multiple-valued logic circuits 用于多值逻辑电路的多结表面隧道晶体管
Proceedings 1997 27th International Symposium on Multiple- Valued Logic Pub Date : 1997-05-28 DOI: 10.1109/ISMVL.1997.601372
T. Baba, T. Uemura
{"title":"Multiple-junction surface tunnel transistors for multiple-valued logic circuits","authors":"T. Baba, T. Uemura","doi":"10.1109/ISMVL.1997.601372","DOIUrl":"https://doi.org/10.1109/ISMVL.1997.601372","url":null,"abstract":"Multiple-junction surface tunnel transistors (MJ-STTs), in which gate-controlled multiple p/sup -//n/sup -/ tunnel-junctions are connected in series between the source and drain, are proposed for application as multiple-valued logic circuits. The transistor operation with four negative-differential-resistance characteristics is confirmed by fabricating a GaAs-based four-tunnel-junction MJ-STT. In addition, to demonstrate the increased functionality of these MJ-STTs, a tri-stable circuit is constructed with an MJ-STT and a load resistor connected in series. Three output voltages (states) are controlled by a reset pulse and successive input pulses applied to the gate of the MJ-STT, confirming the success of the tri-stable operation.","PeriodicalId":206024,"journal":{"name":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132562493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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