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Chairs' welcome message 主席欢迎辞
High Level Design Validation and Test Workshop Pub Date : 2009-11-20 DOI: 10.1109/HLDVT.2009.5340185
P. Kalla, Prabhat Mishra
{"title":"Chairs' welcome message","authors":"P. Kalla, Prabhat Mishra","doi":"10.1109/HLDVT.2009.5340185","DOIUrl":"https://doi.org/10.1109/HLDVT.2009.5340185","url":null,"abstract":"Welcome to the 2009 IEEE International High Level Design Validation and Test Workshop, the 14th in a series of events that explores emerging trends, innovative research and scalable solutions in the areas of validation and test for electronic systems. The two day technical program includes exciting sessions on topics such as design validation approaches at RTL and at system-level, high-level modeling techniques to assist validation, formal verification, and post-silicon validation and debug.","PeriodicalId":204520,"journal":{"name":"High Level Design Validation and Test Workshop","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125870163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Leadership Microprocessors: Validation, debug and test 微处理器:验证、调试和测试
High Level Design Validation and Test Workshop Pub Date : 2009-11-01 DOI: 10.1109/HLDVT.2009.5340187
Sunil R. Shenoy
{"title":"Leadership Microprocessors: Validation, debug and test","authors":"Sunil R. Shenoy","doi":"10.1109/HLDVT.2009.5340187","DOIUrl":"https://doi.org/10.1109/HLDVT.2009.5340187","url":null,"abstract":"I will discuss the use of high level design and abstraction for modeling, simulation and validation of leadership microprocessors, the challenges we have faced in this domain, our learnings and our vision and strategy for the future.","PeriodicalId":204520,"journal":{"name":"High Level Design Validation and Test Workshop","volume":"506 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121322280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Panel: Functional coverage - is your design exposed? 专题讨论:功能覆盖-您的设计是否暴露?
High Level Design Validation and Test Workshop Pub Date : 2005-11-30 DOI: 10.1109/HLDVT.2005.1568845
Andrew Piziali, A. Ziv
{"title":"Panel: Functional coverage - is your design exposed?","authors":"Andrew Piziali, A. Ziv","doi":"10.1109/HLDVT.2005.1568845","DOIUrl":"https://doi.org/10.1109/HLDVT.2005.1568845","url":null,"abstract":"We prove the correctness of an original method for generating components that capture the occurrence of events, and monitor logical and temporal properties of hardware/software embedded systems. The properties are written in PSL, under the form of assertions in declarative form. The method is based on a library of primitive digital components for the PSL temporal operators. These building blocks are interconnected to construct complex properties, resulting in a synthesizable digital module that can be properly linked to the digital system under scrutiny. The proof reported in this paper applies to the weak version of all \"foundation language\" operators.","PeriodicalId":204520,"journal":{"name":"High Level Design Validation and Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116344360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Intel's Post Silicon functional validation approach 英特尔的后硅功能验证方法
High Level Design Validation and Test Workshop Pub Date : 1900-01-01 DOI: 10.1109/HLDVT.2007.4392786
Tommy Bojan, I. Frumkin, R. Mauri
{"title":"Intel's Post Silicon functional validation approach","authors":"Tommy Bojan, I. Frumkin, R. Mauri","doi":"10.1109/HLDVT.2007.4392786","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392786","url":null,"abstract":"CPU Post-Silicon functional validation is the last \"guardian\" logic-wise before delivering the product to the market. In each CPU generation, the challenges are larger due to increasingly complex architectures, budget constraints and shorter schedules. Success can be achieved just with the novel approaches across different validation teams, and with a complex of state-of-the-art validation software, hardware, execution and silicon debug environments. Budget constraints lead to high automation and efficient validation process. Though Intel Corporation has different divisions, mutual help and hard work and optimization ensures high quality product within the schedule.","PeriodicalId":204520,"journal":{"name":"High Level Design Validation and Test Workshop","volume":"526 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114638756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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