{"title":"主席欢迎辞","authors":"P. Kalla, Prabhat Mishra","doi":"10.1109/HLDVT.2009.5340185","DOIUrl":null,"url":null,"abstract":"Welcome to the 2009 IEEE International High Level Design Validation and Test Workshop, the 14th in a series of events that explores emerging trends, innovative research and scalable solutions in the areas of validation and test for electronic systems. The two day technical program includes exciting sessions on topics such as design validation approaches at RTL and at system-level, high-level modeling techniques to assist validation, formal verification, and post-silicon validation and debug.","PeriodicalId":204520,"journal":{"name":"High Level Design Validation and Test Workshop","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Chairs' welcome message\",\"authors\":\"P. Kalla, Prabhat Mishra\",\"doi\":\"10.1109/HLDVT.2009.5340185\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Welcome to the 2009 IEEE International High Level Design Validation and Test Workshop, the 14th in a series of events that explores emerging trends, innovative research and scalable solutions in the areas of validation and test for electronic systems. The two day technical program includes exciting sessions on topics such as design validation approaches at RTL and at system-level, high-level modeling techniques to assist validation, formal verification, and post-silicon validation and debug.\",\"PeriodicalId\":204520,\"journal\":{\"name\":\"High Level Design Validation and Test Workshop\",\"volume\":\"68 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"High Level Design Validation and Test Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HLDVT.2009.5340185\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"High Level Design Validation and Test Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HLDVT.2009.5340185","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Welcome to the 2009 IEEE International High Level Design Validation and Test Workshop, the 14th in a series of events that explores emerging trends, innovative research and scalable solutions in the areas of validation and test for electronic systems. The two day technical program includes exciting sessions on topics such as design validation approaches at RTL and at system-level, high-level modeling techniques to assist validation, formal verification, and post-silicon validation and debug.
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