2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献_第3页

CMOS smart temperature sensors for RFID applications 用于RFID应用的CMOS智能温度传感器

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644858

J. P. M. Brito, A. Rabaeijs

引用次数: 3

Global routing congestion reduction with cost allocation look-ahead 使用预先开销分配减少全局路由拥塞

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644889

L. Nunes, R. Reis

{"title":"Global routing congestion reduction with cost allocation look-ahead","authors":"L. Nunes, R. Reis","doi":"10.1109/SBCCI.2013.6644889","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644889","url":null,"abstract":"This work presents two techniques to define and treat areas that have high interconnection demand in the design of VLSI circuits, during global routing. These techniques are applied in two steps over all global routing flow. The first technique is executed in the pre-routing phase, where are identified regions with a high interconnection density, (there is a large number of sources or destinations reducing its ability to allocate interconnections); the second technique is applied in the iterative routing phase, identifying and protecting those regions from having high congestion, by cost pre-allocation techniques. Three cost pre-allocation parameters were identified and their values are defined on-the-fly, by functions, described in this paper. These techniques were included in an existing global routing flow, called GR-WL, to validate the impact of its implementation, through the extraction of three global routing metrics: wirelength, total value of maximum overflow (TOF) and maximum obtained overflow (MOF). By running experiments using these techniques, total congestion reduction was up to 16%. The results are more relevant when using benchmark circuits for which there is still no valid solutions in the literature. Furthermore, the running times achieved were up to 30% faster when compared to the reference implementation, with a maximum impact of 1.39% in the total wirelength.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130970136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Spin diode network synthesis using functional composition 自旋二极管网络合成的功能组成

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644873

Mayler G. A. Martins, F. Marranghello, J. Friedman, A. Sahakian, R. Ribas, A. Reis

引用次数: 8

Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers 使用高带宽路由器的2D Mesh NoC架构中的高效内存访问

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644857

Jan Heisswolf, Simon Bischof, Michael Rückauer, J. Becker

引用次数: 2

Design of crest factor reduction techniques based on clipping and filtering for wireless communications systems 基于裁剪和滤波的无线通信系统波峰因子降低技术设计

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644874

Pedro F. G. da Silva, E. G. Lima

引用次数: 2

An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs 一种设计热和性能敏感的异构3d - noc的进化方法

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644850

Martha Johanna Sepúlveda, G. Gogniat, R. Pires, J. Wang, M. Strum

{"title":"An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs","authors":"Martha Johanna Sepúlveda, G. Gogniat, R. Pires, J. Wang, M. Strum","doi":"10.1109/SBCCI.2013.6644850","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644850","url":null,"abstract":"Three dimensional Multiprocessor System-on-Chip (3D-MPSoC) adoption. It is characterized by the integration of a large amount of hardware components on a single multilayer chip. However, heating is one of the major pitfalls of the 3D-MPSoCs. Three dimensional Network-on-Chip (3D-NoC) is used as the communication structure of 3D-MPSoCs. Its main role in system operation and performance makes the optimal 3D-NoC design a critical task. Final 3D-NoC configuration must fulfill all the application requirements and heating constraints of the system. Topology and mapping are some of the most critical parameters in 3D-NoC design, strongly influencing the 3D-MPSoC performance and cost. 3D-NoC topology and mapping has been solved for single application systems on homogeneous 3D-NoCs using single and multi-objective optimization algorithms. In this paper we use a multi-objective immune algorithm (MIA), to solve the multi-application 3D-NoC topology and mapping problems. Latency and power consumption are adopted as the target multi-objective functions constrained by the heating function. Our strategy has been applied on 8 3D-MPSoC benchmarks. Their final 3D-NoC configurations have up to 73% power and 42% latency enhancement when compared to previous reported results.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122423934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Combination of radix-2m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers 结合基数-2m乘法器块和加法器压缩器设计高效的2补位64位数组乘法器

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644866

L. Z. Pieper, E. Costa, J. Monteiro

{"title":"Combination of radix-2m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers","authors":"L. Z. Pieper, E. Costa, J. Monteiro","doi":"10.1109/SBCCI.2013.6644866","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644866","url":null,"abstract":"This paper addresses the design of efficient 2's complement 64-bit array multipliers. We propose the combination of radix-2m dedicated multiplier blocks and adder compressors that leads to the reduction of partial product lines, and hence to the higher performance and least power consumption. The flexibility of the architecture allows for the easy construction of multipliers for different values of m. With the use of optimized radix-2m dedicated multiplication blocks the multiplication can be naturally extended up for radix-256 multiplication. Since in the radix-2m multiplier the number of partial lines is reduced, by the multiplication of m bits at a time, we have used a combination of 4:2, 8:2 and 16:2 adder compressors in order to speed-up the addition of the simultaneous operands. We present results of area, delay and power consumption by using SIS and SLS (Switch Level Simulator) tools. The results show that combining the use of dedicated multiplier modules with adder compressors the radix-2m array multipliers are more efficient in terms of delay and power consumption when compared with both a Radix-2m array multiplier with Ripple Carry Adders (RCA) in the partial product lines, previously presented in literature, and the Modified Booth multiplier.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128090995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

An efficient FPGA implementation in quantum-dot cellular automata 量子点元胞自动机的高效FPGA实现

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644867

A. L. P. Marciano, Andre B. Oliveira, J. Nacif, O. V. Neto

引用次数: 2

Hybrid filter for high-power converter systems 用于大功率变换器系统的混合滤波器

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644890

Guilherme H. K. Martini, J. A. Fabro

引用次数: 0

Parallel prefix adder design using quantum-dot cellular automata 基于量子点元胞自动机的并行前缀加法器设计

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644887

Kim A. Escobar, R. Ribas

引用次数: 3