2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献_第2页

A 14b threshold configurable dynamically latched comparator for SAR ADCs 用于SAR adc的14b门限可配置动态锁存比较器

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644886

Tony Forzley, R. Mason

引用次数: 1

Read-polarity-once Boolean functions 读取极性一次的布尔函数

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644862

V. Callegaro, Mayler G. A. Martins, R. Ribas, A. Reis

引用次数: 8

A CMOS bandgap reference circuit with a temperature coefficient adjustment block 带温度系数调节块的CMOS带隙参考电路

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644869

E. Ishibe, J. Navarro

引用次数: 1

A 433/915-MHz class AB discrete power amplifier based on multiresonant circuits 基于多谐振电路的433/915 mhz AB类分立功率放大器

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644855

Fabrício G. S. Silva, R. N. Lima, R. Freire

引用次数: 5

Reducing TMR overhead by combining approximate circuit, transistor topology and input permutation approaches 通过结合近似电路、晶体管拓扑和输入置换方法来降低TMR开销

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644856

I. A. C. Gomes, F. Kastensmidt

引用次数: 13

Analytical logical effort formulation for minimum active area under delay constraints 延迟约束下最小有效面积的解析逻辑努力公式

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644872

Caio G. P. Alegretti, V. D. Bem, R. Ribas, A. Reis

引用次数: 2

Synthesis of a narrow-band Low Noise Amplifier in a 180 nm CMOS technology using Simulated Annealing with crossover operator 基于模拟退火和交叉算子的180nm CMOS窄带低噪声放大器的合成

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644878

T. Weber, Sergio Chaparro, W. Noije

{"title":"Synthesis of a narrow-band Low Noise Amplifier in a 180 nm CMOS technology using Simulated Annealing with crossover operator","authors":"T. Weber, Sergio Chaparro, W. Noije","doi":"10.1109/SBCCI.2013.6644878","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644878","url":null,"abstract":"This paper presents the accurate synthesis of a narrow-band CMOS Low Noise Amplifier (LNA) using an optimization-based approach. Multi-objective information and the corners of the fabrication process are used in the synthesizer to simultaneously optimize impedance matching, performance parameters and circuit robustness. The synthesis approach combines the Simulated Annealing algorithm with the crossover operator and an automatic weight adjustment technique. This combination allows the optimizer to escape local minimums and therefore successfully achieve the LNA specifications. Two solutions of the synthesis are presented and the performance is verified through simulations using a 180 nm CMOS process. The first 2.45 GHz LNA solution achieved a Noise Figure of 1.95 dB, a S21 of 13.6 dB, a S11 of -17 dB, draining a 4.6 mA current. The second solution, which starts from the final first solution and adds a linearity constraint, achieved a Noise Figure of 2.04 dB, a S21 of 12.89 dB, a S11 of -25 dB, a PIIP3 of -7.8 dBm with a current of 4.1 mA. The results indicate the efficiency of the technique to synthesize LNAs, providing solutions comparable to similar presented in the literature.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"2 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120973382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Temporal noise analysis and measurements of CMOS active pixel sensor operating in time domain CMOS有源像素传感器时域噪声分析与测量

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644859

F. S. Campos, J. Ulson, J. Swart, M. Deen, O. Marinov, D. Karam

{"title":"Temporal noise analysis and measurements of CMOS active pixel sensor operating in time domain","authors":"F. S. Campos, J. Ulson, J. Swart, M. Deen, O. Marinov, D. Karam","doi":"10.1109/SBCCI.2013.6644859","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644859","url":null,"abstract":"Image sensors in standard CMOS technology are increasing used for consumer, industrial and scientific applications due to their low cost, high level of integration and low power consumption. Further, image sensors in mainstream complementary metal-oxide-semiconductor (CMOS) technology are preferred because they are the lowest cost and easiest/fastest option to implement. For CMOS image sensors, a key issue is their noise behavior. Therefore, we have studied the noise characteristics of CMOS image sensors operating in time domain. Two important noise sources are the reset noise and integration noise. The reset noise is due to the reset in CMOS image sensors operating in voltage domain. The integration noise is that accumulated during light integration and was found to be the constant, independent of light intensity. Our circuit analysis shows that the signal-to-noise ratio (SNR) is also constant and independent of light intensity. At low light levels the constant SNR is higher compared to others CMOS image sensors presented in the literature. We have implemented a time domain CMOS image sensor in AMS CMOS 0.35um technology. Our measurements results show that the SNR level is approximately constant to 43dB.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"123 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114010182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation 低vdd /高vdd对SAD计算的影响

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644880

Ismael Seidel, Bruno George de Moraes, André Beims Bräscher, José Luís Almada Güntzel

{"title":"On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation","authors":"Ismael Seidel, Bruno George de Moraes, André Beims Bräscher, José Luís Almada Güntzel","doi":"10.1109/SBCCI.2013.6644880","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644880","url":null,"abstract":"As the number of pixels per frame tends to increase in new high definition video coding standards such as HEVC, pel decimation appears as a viable means of increasing the energy efficiency of Sum of Absolute Differences (SAD) calculation. This paper presents a VLSI architecture that can be configured to compute the SAD of 4×4 pixel blocks with no subsampling or with 2:1 or 4:1 subsampling (pel decimation). The proposed architecture was synthesized for 130nm, 90nm, 65nm and 45nm standard cell libraries assuming both nominal and Low-Vdd/High-Vt (LH) cases for maximum and a given target throughput. The impacts of subsampling and Low-Vdd/High-Vt on delay, power and energy efficiency are analyzed. In a total of 16 syntheses, the 45nm/LH configurable SAD architecture achieved the highest energy efficiency for target frequency when operating in pel decimation 4:1, spending only 2.19pJ for each 4×4 block, which corresponds to about 20.64 times less energy than the 130nm/nominal configurable architecture operating in full SAD mode. Aside the improvements achieved by using LH, pel decimation solely was responsible for energy reductions of 40% and 60% when 2:1 and 4:1 subsamplings are chosen, respectively, in the configurable architecture.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127634762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

H2A: A hardened asynchronous network on chip H2A:一个强化的异步片上网络

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2013-10-24 DOI: 10.1109/SBCCI.2013.6644865

Julian J. H. Pontes, Ney Laert Vilar Calazans, P. Vivet

{"title":"H2A: A hardened asynchronous network on chip","authors":"Julian J. H. Pontes, Ney Laert Vilar Calazans, P. Vivet","doi":"10.1109/SBCCI.2013.6644865","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644865","url":null,"abstract":"One of the next challenges for asynchronous communication architectures is reliability, in the form of robustness to single event effects, when under the impact of particles generated by ionizing radiation. This occurs because technology down-scaling continuously increases the logic sensitivity of silicon devices to such effects. Contrary to what happens in synchronous circuits, delay variations induced by radiation usually have no impact on asynchronous quasi-delay insensitive (QDI) combinational logic blocks, but in case of storage logic, bit flips may corrupt the circuit state with no recovery solution, even when using asynchronous circuits. This work proposes a new set of hardening techniques against single event effects applicable to asynchronous networks-on-chip. It presents practical case studies of use for these techniques and evaluates them in close to real life situations. Obtained results show that the achieved increase in asynchronous network-on-chip robustness has the potential to leverage this communication architecture solution as the main choice for the next generations of complex silicon devices on advanced nodes technologies such as 32 nm, 28 nm and below.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122855179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1