Analytical logical effort formulation for minimum active area under delay constraints

Abstract

This paper presents a gate sizing method which formulates minimum active area solutions under delay constraints. The method is based on the logical effort delay model. The minimization of transistor widths has direct impact on the power consumption and circuit area reduction. The analytical formulation of the method takes into account the maximum input capacitance, the load to be driven, and the given timing constraint. Electrical simulations show that the proposed method is very precise for a first order approach, as it presents small average errors of 1.48% in power dissipation, 2.28% in delay propagation, and 6.5% in transistor sizes.