An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs

Three dimensional Multiprocessor System-on-Chip (3D-MPSoC) adoption. It is characterized by the integration of a large amount of hardware components on a single multilayer chip. However, heating is one of the major pitfalls of the 3D-MPSoCs. Three dimensional Network-on-Chip (3D-NoC) is used as the communication structure of 3D-MPSoCs. Its main role in system operation and performance makes the optimal 3D-NoC design a critical task. Final 3D-NoC configuration must fulfill all the application requirements and heating constraints of the system. Topology and mapping are some of the most critical parameters in 3D-NoC design, strongly influencing the 3D-MPSoC performance and cost. 3D-NoC topology and mapping has been solved for single application systems on homogeneous 3D-NoCs using single and multi-objective optimization algorithms. In this paper we use a multi-objective immune algorithm (MIA), to solve the multi-application 3D-NoC topology and mapping problems. Latency and power consumption are adopted as the target multi-objective functions constrained by the heating function. Our strategy has been applied on 8 3D-MPSoC benchmarks. Their final 3D-NoC configurations have up to 73% power and 42% latency enhancement when compared to previous reported results.