2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)最新文献_第5页

FIESTA-EXTRA: cell-oriented software for the defect/fault analysis in VLSI circuits fista - extra:用于VLSI电路缺陷/故障分析的面向单元的软件

2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314953

A. Blyzniuk, I. Kazymyra

引用次数: 4

Shift register based TPG for at-speed interconnect BIST 基于移位寄存器的TPG高速互连BIST

2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314941

A. Jutman

引用次数: 8

CMOS analog design for wireless communication 无线通信的CMOS模拟设计

2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314882

V. Liberali, G. Trucco

引用次数: 0

Feasibility study of low-swing clocking 低摆频时钟的可行性研究

2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314884

Dejan Markovic, J. Tschanz, Vivek De

{"title":"Feasibility study of low-swing clocking","authors":"Dejan Markovic, J. Tschanz, Vivek De","doi":"10.1109/ICMEL.2004.1314884","DOIUrl":"https://doi.org/10.1109/ICMEL.2004.1314884","url":null,"abstract":"This paper evaluates the feasibility of low-swing clocking under no performance degradation constraint. We consider flip-flops, logic and clock distribution network in our analysis. The preferred flip-flop topologies for low-swing clocking (low-V/sub Clk/) are different from those normally used in a full-swing (high-V/sub Clk/) design. Clock buffers are redesigned to accommodate reduced drive current under low-V/sub Clk/. In order to maintain performance, logic and flip-flops must absorb increase in clock skew due to low-V/sub Clk/. In a 64-bit ALU design, the optimal low-V/sub Clk/ design point is at the minimum energy-delay product (EDP) point of the high-V/sub Clk/ design, with no delay or energy penalty in the ALU itself. A 43% energy reduction achieved in the clock distribution network results in a 13% overall energy savings due to low-V/sub Clk/, assuming that the clocking energy is 40% of the total energy tinder high-V/sub Clk/. For performance targets of at least one FO4 inverter delay better than the min-EDP point, low-swing clocking becomes ineffective because of a high energy cost in logic that is spent to absorb increase in flip-flop delay and clock skew. Finally, low-V/sub Clk/ cannot achieve the peak performance of the high-V/sub Clk/ design due to slower flip-flops and higher clock uncertainty at low-V/sub Clk/.","PeriodicalId":202761,"journal":{"name":"2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127608413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Radioactive resistance of some commercial memory components 一些商用存储器元件的耐放射性

2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314928

B. Loncar, S. Stankovic, P. Osmokrović

引用次数: 0

A case study of SPC in circuit board assembly: statistical mounting process control SPC在电路板组装中的案例研究:统计安装过程控制

2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314857

T. Liukkonen, A. Tuominen

{"title":"A case study of SPC in circuit board assembly: statistical mounting process control","authors":"T. Liukkonen, A. Tuominen","doi":"10.1109/ICMEL.2004.1314857","DOIUrl":"https://doi.org/10.1109/ICMEL.2004.1314857","url":null,"abstract":"A system was developed to continuously monitor the cycle times of successive placement machines in a long high-speed surface mount line. Statistical process control software was created to generate predefined out-of-control alarms when an unexpected change is monitored in the cycle times. The developed Statistical Mounting Process Control application was divided into three monitoring levels: line performance view, machine performance view, and pickup performance view (i.e, component feeders and nozzles). Most of the problems causing unexpected increase in placement cycle time are directly related to bad performing feeders or nozzles. The data transfer between the machines and host computer system is described. Out-of-control criterias selected for this statistical process control application are discussed in detail. One typical out-of-control situation is described for fast action and response to get the placement - process back to right track again. Promising results were observed after several weeks of evaluation of the system in two production lines: component pickup errors were decreased about 50%. In the future this is expected to have a direct positive impact on the output of the factory as well as on the total material cost and unexpected shortages, because component waste is simultaneously decreased. A theory is also discussed about poor pick-up performance having possible negative effect on the placement accuracy.","PeriodicalId":202761,"journal":{"name":"2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117033539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

High speed circuits for genetics applications 用于遗传学应用的高速电路

2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314878

S. Bojanic, G. Caffarena, C. Pedreira, O. Nieto-Taladriz

引用次数: 3

Hot-carrier induced degradation of offset gated polysilicon TFTs 偏置门控多晶硅tft的热载流子诱导降解

2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314925

A. Hatzopoulos, C. Dimitriadis, G. Pananakakis, G. Ghibaudo, G. Kamarinos

引用次数: 0

MEMS tunable capacitors and switches for RF applications 用于射频应用的MEMS可调电容器和开关

2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314557

T. Rijks, J. V. van Beek, P. Steeneken, M. Ulenaers, P. van Eerd, J. den Toonder, A. van Dijken, J. de Coster, R. Puers, J. Weekamp, J. Scheer, A. Jourdain, H. Tilmans

引用次数: 14

Electrical characterization of Ni/sub y/(Si/sub 1-x/Ge/sub x/)/sub 1-y//Si/sub 1-x/Ge/sub x/ and NiSi/Si Schottky diodes Ni/sub y/(Si/sub 1-x/Ge/sub x/)/sub 1-y//Si/sub 1-x/Ge/sub x/和NiSi/Si肖特基二极管的电学特性

2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI: 10.1109/ICMEL.2004.1314651

A. Saha, S. Chattopadhyay, G. Dalapati, S. Nandi, C. K. Maiti

引用次数: 1