N. Karagiorgos, N. Nenadis, D. Trypidis, K. Siozios, S. Siskos, S. Nikolaidis, M. Tsimidou
{"title":"An approach for estimating adulteration of virgin olive oil with soybean oil using image analysis","authors":"N. Karagiorgos, N. Nenadis, D. Trypidis, K. Siozios, S. Siskos, S. Nikolaidis, M. Tsimidou","doi":"10.1109/MOCAST.2017.7937672","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937672","url":null,"abstract":"This paper describes the development of an image processing algorithm, which can estimate the amount of adulteration of olive oil with soybean oil from a captured photo. This algorithm is intended to be implemented into an application for modern smartphones, where the user can measure the quality of a sample of olive oil, only by taking photos from the sample. The determination of the adulteration percentage is done by separating the captured image into two regions: one that contains only the oil sample and another one, which contains the rest of the image. The colour difference between these two regions, for known adulteration percentages is used to determine the appropriate model that combines these quantities. Then, any other mixture of these oils, can be identified using the derived model and the methodology that is described in this paper.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133715471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Grassi, A. Ouannas, A. Azar, A. Radwan, C. Volos, V. Pham, T. Ziar, A. Madian, I. Kyprianidis, I. Stouboulos
{"title":"Chaos synchronisation of continuous systems via scalar signal","authors":"G. Grassi, A. Ouannas, A. Azar, A. Radwan, C. Volos, V. Pham, T. Ziar, A. Madian, I. Kyprianidis, I. Stouboulos","doi":"10.1109/MOCAST.2017.7937629","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937629","url":null,"abstract":"By analyzing the issue of chaos synchronization in the literature, it can be noticed the lack of a general approach, which would enable any type of synchronization to be achieved. Similarly, there is the lack of a unified method for synchronizing both continuous-time and discrete-time systems via a scalar signal. This paper and the companion one [1] aim to bridge these two gaps by presenting a novel general unified framework to synchronize chaotic systems via a scalar signal. The framework, based on the concept of observer, enables any type of synchronization defined to date to be achieved for both continuous-time and discrete-time systems via a scalar signal. This paper focuses on continuous-time systems, while the companion paper [1] deals with discrete-time systems. Herein, the observer-based framework exploits a structural condition related to the uncontrollable eigenvalues of the error system. Several examples of different types of synchronization are illustrated, with the aim to show the capabilities of the approach.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133479071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Christos I. Salis, T. Zygiridis, P. Sarigiannidis, N. Kantartzis
{"title":"A stochastic FDTD approach for assessing random media uncertainties in polar coordinates","authors":"Christos I. Salis, T. Zygiridis, P. Sarigiannidis, N. Kantartzis","doi":"10.1109/MOCAST.2017.7937648","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937648","url":null,"abstract":"Deterministic schemes are usually unable to predict random media uncertainties and as a result produce unreliable outcomes in this kind of problems. In this work, we present a novel finite difference time domain (FDTD) technique that manages to calculate the statistics of the involved field quantities, considering that the variability of random media is known. The proposed method is applied in polar grids and can efficiently deal with such cases in a single realization. Comparisons with the Monte Carlo method show that reliable results may be obtained, thus making our proposed technique much more faster.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121928003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A time-aware code execution continuous monitoring for safety-critical applications","authors":"Vasileios Chioktour, A. Kakarountas","doi":"10.1109/MOCAST.2017.7937615","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937615","url":null,"abstract":"The introduction of novel safety-critical applications in our day-to-day life, have increased significantly the requirement of developing systems that embed sophisticated mechanisms to ensure safe operation. The most challenging task is continuous monitoring to detect erroneous operation. The introduction of new safety standards has urged the need for novel design approaches towards safety operation. In this paper, a new technique to achieve continuous monitoring of code execution is proposed, ensuring both spatial (in terms of memory) and temporal constraints.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122369280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Elias Koromilas, I. Stamelos, C. Kachris, D. Soudris
{"title":"Spark acceleration on FPGAs: A use case on machine learning in Pynq","authors":"Elias Koromilas, I. Stamelos, C. Kachris, D. Soudris","doi":"10.1109/MOCAST.2017.7937637","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937637","url":null,"abstract":"Spark is one of the most widely used frameworks for data analytics. Spark allows fast development for several applications like machine learning, graph computations, etc. In this paper, we present Spynq: A framework for the efficient deployment of data analytics on embedded systems that are based on the heterogeneous MPSoC FPGA called Pynq. The mapping of Spark on Pynq allows that fast deployment of embedded and cyber-physical systems that are used in edge and fog computing. The proposed platform is evaluated in a typical machine learning application based on logistic regression. The performance evaluation shows that the heterogeneous FPGA-based MPSoC can achieve up to 11× speedup compared to the execution time in the ARM cores and can reduce significantly the development time of embedded and cyber-physical systems on Spark applications.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128941815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Enrico Lovisotto, E. Vianello, Davide Cazzaro, Michele Polese, Federico Chiariotti, Daniel Zucchetto, A. Zanella, M. Zorzi
{"title":"Cell traffic prediction using joint spatio-temporal information","authors":"Enrico Lovisotto, E. Vianello, Davide Cazzaro, Michele Polese, Federico Chiariotti, Daniel Zucchetto, A. Zanella, M. Zorzi","doi":"10.1109/MOCAST.2017.7937674","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937674","url":null,"abstract":"In future cellular networks, the ability to predict network parameters such as cell load will be a key enabler of several proposed adaptation and resource allocation techniques. In this study, we consider a joint exploitation of spatio-temporal data to improve the prediction accuracy of standard regression methods. We test several such methods from the literature on a publicly available dataset and document the advantages of the proposed approach.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126133935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Annovi, G. Calderini, F. Crescioli, F. Canio, L. Frontini, T. Kubota, V. Liberali, P. Luciano, F. Palla, S. Shojaii, C. Sotiropoulou, A. Stabile, G. Traversi
{"title":"A low-power and high-density Associative Memory in 28 nm CMOS technology","authors":"A. Annovi, G. Calderini, F. Crescioli, F. Canio, L. Frontini, T. Kubota, V. Liberali, P. Luciano, F. Palla, S. Shojaii, C. Sotiropoulou, A. Stabile, G. Traversi","doi":"10.1109/MOCAST.2017.7937632","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937632","url":null,"abstract":"In this paper we present a new Associative Memory (AM) chip designed in the 28 nm TSMC HPL technology. Two of the main characteristics of the new chip are reduced power consumption and an increased memory cell area density by the use of two newly designed memory cell technologies. The aim of the new chip is to test the new technologies with realistic front-end functions. The integration of the AM and FPGA is also enhanced. In addition, LVDS drivers and receivers are implemented to strengthen the signal integrity of the I/Os. The new AM chip design is submitted for the fabrication. The die will be packaged in a 17 × 17 Ball Grid Array (BGA) standalone package with a Silicon In Package (SiP) structure mounting AM dies and a bare die FPGA.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125638885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Mirzaei, V. Voisin, A. Annovi, G. Baulieu, M. Beretta, G. Calderini, S. Citraro, F. Crescioli, G. Galbit, V. Liberali, S. Shojaii, A. Stabile, W. Tromeur, S. Viret
{"title":"Heterogeneous computing system platform for high-performance pattern recognition applications","authors":"M. Mirzaei, V. Voisin, A. Annovi, G. Baulieu, M. Beretta, G. Calderini, S. Citraro, F. Crescioli, G. Galbit, V. Liberali, S. Shojaii, A. Stabile, W. Tromeur, S. Viret","doi":"10.1109/MOCAST.2017.7937638","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937638","url":null,"abstract":"we present a system architecture made of a motherboard with a Xilinx Zynq System on Chip (SoC) and a mezzanine board equipped with an Associative Memory chip (AM). The proposed architecture is designed to serve as an accelerator of general purpose algorithms based on pipeline processing and pattern recognition. We present the open source software and firmware developed to fully exploit the available communication channels between the ARM CPU and the FPGA using Direct Memory Access (DMA) technique and the AM using Multi-Gigabit Transceivers (MGT). We report the measured performances and discuss potential applications and future developments. The proposed architecture is compact, portable and provide a large communication bandwidth between components.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"33 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134529188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Vourkas, Angel Abusleme, Nikolaos Vasileiadis, G. Sirakoulis, N. Papamarkos
{"title":"Towards memristive crossbar-based neuromorphic HW accelerators for signal processing","authors":"I. Vourkas, Angel Abusleme, Nikolaos Vasileiadis, G. Sirakoulis, N. Papamarkos","doi":"10.1109/MOCAST.2017.7937678","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937678","url":null,"abstract":"Research progress in neuromorphic hardware, capable of biological perception and cognitive information processing, is leading the way towards a revolution in computing technology. Current research efforts have focused mainly on resistive switching devices, the electronic analog of synapses in artificial neural networks (ANNs), and the crossbar nanoarchitecture, for its huge connectivity and maximum integration density. In this context, this work presents the design and simulation of a memristive crossbar-based ANN for text recognition tasks, implementing a novel computing algorithm. In such case study, important issues during the application mapping process are identified and properly addressed at device and circuit level. The computing capabilities of the proposed system are highlighted through SPICE-level circuit simulations, which show excellent agreement with theoretical simulation results.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"55 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134547647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Recursive odd-even sorter for vector quantizer","authors":"Berkin Atila, B. Kelleci","doi":"10.1109/MOCAST.2017.7937665","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937665","url":null,"abstract":"A recursive, odd-even transposition sorter based vector quantizer which is used in mismatch shaping algorithms is presented. Although recursive parallel sorting algorithms require less area than fully parallel sorting algorithms, they are slower than fully parallel algorithms. A widely used recursive parallel sorting algorithm is the perfect shuffle which requires multiple clock cycles to shuffle and sort the data. The proposed recursive algorithm uses fewer clock cycles than the perfect shuffle to sort less than 80 inputs. An area efficient version is also proposed to sort less than 16 inputs faster than perfect shuffle algorithm. To compare the performance of various sorting algorithms suitable for vector quantizer, they are realized and synthesized in TSMC 40nm low-power technology. Speed and area results indicate that the proposed algorithm sorts 32 inputs at a 42% faster rate by using 14% fewer components than the perfect shuffle sorter and a 80% slower rate by using 27% fewer components than the Bitonic sorter. The area efficient version sorts 32 inputs at a 21% slower rate by using 32% fewer components than the perfect shuffle sorter.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"30 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134552302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}