Proceedings Seventeenth Conference on Advanced Research in VLSI最新文献_第2页

Compact signed-digit adder using multiple-valued logic 使用多值逻辑的紧凑符号数字加法器

Proceedings Seventeenth Conference on Advanced Research in VLSI Pub Date : 1997-09-15 DOI: 10.1109/ARVLSI.1997.634849

Alejandro F. González, P. Mazumder

{"title":"Compact signed-digit adder using multiple-valued logic","authors":"Alejandro F. González, P. Mazumder","doi":"10.1109/ARVLSI.1997.634849","DOIUrl":"https://doi.org/10.1109/ARVLSI.1997.634849","url":null,"abstract":"As minimum feature sizes shrink and the number of transistors integrated in a single chip grow, interconnect complexity is one of the most important issues to be solved in future VLSI chips. The use of multivalued logic is one way to effectively solve this problem because multiple-valued signals convey more information than binary signals and thus, require a lower number of interconnecting wires to achieve similar bandwidths. This paper describes a new signed-digit adder design, which uses multiple-valued logic. The circuit is composed of resonant-tunneling diodes (RTDs) and MOS transistors. The negative differential-resistance (NDR) characteristics of RTDs help to achieve very compact circuits for implementing the multiple-valued functions found in signed-digit adders, MOS transistors are useful for implementing current-mode logic, in which addition of two or more signals is performed by simple wire interconnection. Since a redundant arithmetic is being used the selected transfer functions allow the proposed circuit to perform addition where no ripple-carry effect is present. The design was verified using circuit simulation. To demonstrate the validity of the principles being used, a modified prototype of the circuit was built. In the prototype, a standard 2-micron CMOS process was used to fabricate the MOS-based circuitry while RTDs were connected externally. Even though no fabrication processes which integrate RTDs and MOS devices are currently available, there are efforts on the development of such technologies so that the advantages of these devices can be combined.","PeriodicalId":201675,"journal":{"name":"Proceedings Seventeenth Conference on Advanced Research in VLSI","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116789625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Image edge enhancement, dynamic compression and noise suppression using analog circuit processing 图像边缘增强、动态压缩和噪声抑制采用模拟电路处理

Proceedings Seventeenth Conference on Advanced Research in VLSI Pub Date : 1997-09-15 DOI: 10.1109/ARVLSI.1997.634850

T. Hinck, A. Hubbard

引用次数: 2

Signal delay in coupled, distributed RC lines in the presence of temporal proximity 在时间接近的情况下，耦合、分布式RC线的信号延迟

Proceedings Seventeenth Conference on Advanced Research in VLSI Pub Date : 1997-09-15 DOI: 10.1109/ARVLSI.1997.634844

V. Chandramouli, K. Sakallah, A. Kayssi

引用次数: 0

Next-generation RF circuits and systems 下一代射频电路和系统

Proceedings Seventeenth Conference on Advanced Research in VLSI Pub Date : 1997-09-15 DOI: 10.1109/ARVLSI.1997.634859

B. Razavi

引用次数: 4

Interfacing synchronous and asynchronous modules within a high-speed pipeline 在高速管道内连接同步和异步模块

Proceedings Seventeenth Conference on Advanced Research in VLSI Pub Date : 1997-09-15 DOI: 10.1109/ARVLSI.1997.634845

Allen E. Sjogren, C. Myers

{"title":"Interfacing synchronous and asynchronous modules within a high-speed pipeline","authors":"Allen E. Sjogren, C. Myers","doi":"10.1109/ARVLSI.1997.634845","DOIUrl":"https://doi.org/10.1109/ARVLSI.1997.634845","url":null,"abstract":"This paper describes a new technique for integrating asynchronous modules within a high-speed synchronous pipeline. Our design eliminates potential metastability problems by using a clock generated by a stoppable ring oscillator, which is capable of driving the large clock load found in present day microprocessors. Using the ATACS design tool, we designed highly optimized transistor-level circuits to control the ring oscillator and generate the clock and handshake signals with minimal overhead. Our interface architecture requires no redesign of the synchronous circuitry. Incorporating asynchronous modules in a high-speed pipeline improves performance by exploiting data-dependent delay variations. Since the speed of the synchronous circuitry tracks the speed of the ring oscillator under different processes, temperatures, and voltages, the entire chip operates at the speed dictated by the current operating conditions, rather than being governed by the worst-case conditions. These two factors together can lead to a significant improvement in average-case performance. The interface design is tested using the 0.6 /spl mu/m HP CMOS14B process in HSPICE.","PeriodicalId":201675,"journal":{"name":"Proceedings Seventeenth Conference on Advanced Research in VLSI","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127911862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 91

Design implementation of intrinsic area array ICs 本构面积阵列集成电路的设计实现

Proceedings Seventeenth Conference on Advanced Research in VLSI Pub Date : 1997-09-15 DOI: 10.1109/ARVLSI.1997.634848

C. Tan, D. Bouldin, P. Dehkordi

引用次数: 13

Kestrel: design of an 8-bit SIMD parallel processor 红隼:一个8位SIMD并行处理器的设计

Proceedings Seventeenth Conference on Advanced Research in VLSI Pub Date : 1997-09-15 DOI: 10.1109/ARVLSI.1997.634852

David M. Dahle, Jeffrey D. Hirschberg, K. Karplus, H. Keller, Eric Rice, D. Speck, Douglas H. Williams, R. Hughey

{"title":"Kestrel: design of an 8-bit SIMD parallel processor","authors":"David M. Dahle, Jeffrey D. Hirschberg, K. Karplus, H. Keller, Eric Rice, D. Speck, Douglas H. Williams, R. Hughey","doi":"10.1109/ARVLSI.1997.634852","DOIUrl":"https://doi.org/10.1109/ARVLSI.1997.634852","url":null,"abstract":"Kestrel is a high-performance programmable parallel co-processor. Its design is the result of examination and reexamination of algorithmic, architectural, packaging, and silicon design issues, and the interrelations between them. The final system features a linear array of 8-bit processing elements, each with local memory, an arithmetic logic unit (ALU), a multiplier, and other functional units. Sixty-four Kestrel processing elements fit in a 1.4 million transistor, 60 mm/sup 2/, 0.5 /spl mu/m CMOS chip with just 84 pins. The planned single-board, 8-chip system will, for some applications, provide supercomputer performance at a fraction of the cost. This paper surveys four of our applications (sequence analysis, neural networks, image compression, and floating-point arithmetic), and discusses the philosophy behind many of the design comparator's compact instruction encoding and design, the architecture's facility with nested conditionals, and the multiplier's flexibility in performing multiprecision operations. Finally, we discuss the implementation and performance of the Kestrel test chips.","PeriodicalId":201675,"journal":{"name":"Proceedings Seventeenth Conference on Advanced Research in VLSI","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117218346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Clock distribution using cooperative ring oscillators 时钟分配使用合作环振荡器

Proceedings Seventeenth Conference on Advanced Research in VLSI Pub Date : 1997-09-15 DOI: 10.1109/ARVLSI.1997.634846

L. Hall, M. Clements, Wentai Liu, G. Bilbro

引用次数: 25

A VLSI architecture for modeling intersegmental coordination 一种用于段间协调建模的VLSI体系结构

Proceedings Seventeenth Conference on Advanced Research in VLSI Pub Date : 1997-09-15 DOI: 10.1109/ARVLSI.1997.634854

S. DeWeerth, G. Patel, M. Simoni, D. Schimmel, R. Calabrese

引用次数: 16

Asynchronous microengines for efficient high-level control 异步微引擎，高效的高层控制

Proceedings Seventeenth Conference on Advanced Research in VLSI Pub Date : 1997-09-15 DOI: 10.1109/ARVLSI.1997.634855

H. Jacobson, G. Gopalakrishnan

{"title":"Asynchronous microengines for efficient high-level control","authors":"H. Jacobson, G. Gopalakrishnan","doi":"10.1109/ARVLSI.1997.634855","DOIUrl":"https://doi.org/10.1109/ARVLSI.1997.634855","url":null,"abstract":"Asynchronous (self-timed) circuits are quite natural for realizing control-intensive designs. Many such designs are of reactive nature and inherently complex due to complicated communication protocols. In these situations programmable controllers are preferable over hardwired controllers to allow design decisions to be bound late, help connect errors that may slip through the verification process, and even permit run-time modification of control algorithms to best suit the current situation. Virtually all recent work in asynchronous controller design focuses on generating hardwired controllers. In this paper, we propose an architecture for programmable asynchronous controllers in the form m of microprogrammed asynchronous \"microengine\". Architectures utilizing both two-phase and four-phase handshaking are proposed. The datapath structure of the asynchronous microengine is modular and easily extensible, facilitating changes during the design phase. We ensure high performance of the asynchronous microengine by exploiting concurrency between operations and employ efficient control structures. Initial results show that the proposed microengine can yield performance close to that offered by automated high-level synthesis tools targeting custom hardwired burst-mode machines for control.","PeriodicalId":201675,"journal":{"name":"Proceedings Seventeenth Conference on Advanced Research in VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115474801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2