Compact signed-digit adder using multiple-valued logic

Abstract

As minimum feature sizes shrink and the number of transistors integrated in a single chip grow, interconnect complexity is one of the most important issues to be solved in future VLSI chips. The use of multivalued logic is one way to effectively solve this problem because multiple-valued signals convey more information than binary signals and thus, require a lower number of interconnecting wires to achieve similar bandwidths. This paper describes a new signed-digit adder design, which uses multiple-valued logic. The circuit is composed of resonant-tunneling diodes (RTDs) and MOS transistors. The negative differential-resistance (NDR) characteristics of RTDs help to achieve very compact circuits for implementing the multiple-valued functions found in signed-digit adders, MOS transistors are useful for implementing current-mode logic, in which addition of two or more signals is performed by simple wire interconnection. Since a redundant arithmetic is being used the selected transfer functions allow the proposed circuit to perform addition where no ripple-carry effect is present. The design was verified using circuit simulation. To demonstrate the validity of the principles being used, a modified prototype of the circuit was built. In the prototype, a standard 2-micron CMOS process was used to fabricate the MOS-based circuitry while RTDs were connected externally. Even though no fabrication processes which integrate RTDs and MOS devices are currently available, there are efforts on the development of such technologies so that the advantages of these devices can be combined.