S. DeWeerth, G. Patel, M. Simoni, D. Schimmel, R. Calabrese
{"title":"一种用于段间协调建模的VLSI体系结构","authors":"S. DeWeerth, G. Patel, M. Simoni, D. Schimmel, R. Calabrese","doi":"10.1109/ARVLSI.1997.634854","DOIUrl":null,"url":null,"abstract":"A hybrid analog/digital VLSI architecture that models the coordination of neurobiological segmental oscillators is presented. This architecture facilitates the modeling of systems such as those that produce swimming in vertebrates and fish, as well as motivates the creation of a class of biologically inspired, \"intelligent\" motion-control systems. The two primary components of the architecture are described: intrasegmental oscillators that consist of neurons and synapses that are implemented primarily rising analog VLSI circuits; and an intersegmental communication network that is implemented, primarily rising asynchronous digital circuits. Preliminary test results are presented to demonstrate the operation of the system and its components.","PeriodicalId":201675,"journal":{"name":"Proceedings Seventeenth Conference on Advanced Research in VLSI","volume":"88 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A VLSI architecture for modeling intersegmental coordination\",\"authors\":\"S. DeWeerth, G. Patel, M. Simoni, D. Schimmel, R. Calabrese\",\"doi\":\"10.1109/ARVLSI.1997.634854\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A hybrid analog/digital VLSI architecture that models the coordination of neurobiological segmental oscillators is presented. This architecture facilitates the modeling of systems such as those that produce swimming in vertebrates and fish, as well as motivates the creation of a class of biologically inspired, \\\"intelligent\\\" motion-control systems. The two primary components of the architecture are described: intrasegmental oscillators that consist of neurons and synapses that are implemented primarily rising analog VLSI circuits; and an intersegmental communication network that is implemented, primarily rising asynchronous digital circuits. Preliminary test results are presented to demonstrate the operation of the system and its components.\",\"PeriodicalId\":201675,\"journal\":{\"name\":\"Proceedings Seventeenth Conference on Advanced Research in VLSI\",\"volume\":\"88 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Seventeenth Conference on Advanced Research in VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARVLSI.1997.634854\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Seventeenth Conference on Advanced Research in VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARVLSI.1997.634854","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A VLSI architecture for modeling intersegmental coordination
A hybrid analog/digital VLSI architecture that models the coordination of neurobiological segmental oscillators is presented. This architecture facilitates the modeling of systems such as those that produce swimming in vertebrates and fish, as well as motivates the creation of a class of biologically inspired, "intelligent" motion-control systems. The two primary components of the architecture are described: intrasegmental oscillators that consist of neurons and synapses that are implemented primarily rising analog VLSI circuits; and an intersegmental communication network that is implemented, primarily rising asynchronous digital circuits. Preliminary test results are presented to demonstrate the operation of the system and its components.