Signal delay in coupled, distributed RC lines in the presence of temporal proximity

V. Chandramouli, K. Sakallah, A. Kayssi
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Abstract

With improvements in technology, accurate delay modeling of interconnects is becoming increasingly important. Due to decreasing feature sizes, the spacing between the signal lines is also decreasing. Consequently, the switching activities on the neighboring lines can have a significant impact on the delay of the line of interest, and can no longer be ignored. Accurate modeling of this phenomenon, which we call the proximity effect, is the subject of this paper. This is similar to the state-dependency of logic gate delays, where signal delay can be affected by the switching activities on the side inputs of a gate. We describe an efficient and accurate delay computation method using precomputed interconnect moments that treats the coupled lines as uniform, distributed RC lines and does not make any lumped approximations. This allows the proposed delay model to be used in a timing analysis tool operating over both gate and interconnect domains while accounting for state-dependency.
在时间接近的情况下,耦合、分布式RC线的信号延迟
随着技术的进步,准确的互连延迟建模变得越来越重要。由于特征尺寸的减小,信号线之间的间距也在减小。因此,相邻线路上的切换活动会对感兴趣线路的延迟产生重大影响,不能再忽略。这种现象的精确建模,我们称之为邻近效应,是本文的主题。这类似于逻辑门延迟的状态依赖性,其中信号延迟可能受到门侧输入上的开关活动的影响。我们描述了一种有效而准确的延迟计算方法,使用预先计算的互连矩,将耦合线视为均匀分布的RC线,不做任何集中近似。这使得所提出的延迟模型可用于在门域和互连域上操作的时序分析工具,同时考虑状态依赖性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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