2018 7th Electronic System-Integration Technology Conference (ESTC)最新文献

{"title":"Light-weight Compressible and Highly Thermal Conductive Graphene-based Thermal Interface Material","authors":"Nan Wang, Shujin Chen, Amos Nkansah, L. Ye, Johan Liu","doi":"10.1109/ESTC.2018.8546453","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546453","url":null,"abstract":"High density packaging in combination with increased transistor integration inevitably leads to challenging power densities in terms of thermal management. Thermal interface materials (TIMs) play a key role in thermal management by transferring heat from the surface of power devices. The conventional TIMs used in the microelectronics industry today basically are particle laden polymer matrix composites, which have the advantages of good reliability and ease of use. However, the thermal conductivity (K) of these composites is generally limited to 10 W/mK, which is hard to meet the goal for efficient thermal management in power devices. Here, we solve the problem by applying a novel highly thermal conductive and compressible graphene based TIMs (GTs). Composed by vertical graphene structures, GTs provide a continuous high thermal conductivity phase along the path of thermal transport, which lead to outstanding thermal properties. By tailoring ratios of graphene in the polymer binder, bulk thermal conductivity of GTs can be varied from 50 to 1000 W/mK. This result isorders of magnitude higher than conventional TIMs, and even outperforms the pure indium TIMs by over ten times. Meanwhile, the highly flexible and foldable nature of vertical graphene enables at least 20% compressibility of the GTs upon small applied pressures ($le$ 400 KPa). As excellent gap fillers, GT can provide complete physical contact between two surfaces and thereby minimize the contact resistance to heat flow. The measured minimum thermal resistance and maximum effective thermal conductivity for GTs reaches to $sim $ Kmm$^{2}$/W and $sim mathrm{W} /$mK, respectively. Such values are significantly higher than the randomly dispersed composites presented above, and show almost comparable thermal performance as pure indium bonding. In addition, the GTs has more advantages than indium/solder bonding, including low weight (density $lt2mathrm{g} /$cm}$^{3}$), low complexity during assembly and maintainability. The resulting GTs thus opens new opportunities for addressing large heat dissipation issues both in through-plane and in-plane directions for form-factor driven electronics and other high power driven systems.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115626487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ESTC 2018 Index","authors":"","doi":"10.1109/estc.2018.8546460","DOIUrl":"https://doi.org/10.1109/estc.2018.8546460","url":null,"abstract":"","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123526917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"How my electronics should be oriented: A thermal point of view study to understand the impact of orientation on internal air temperature","authors":"Tejas Manohar Kesarkar, Nitesh Kumar Sardana","doi":"10.1109/ESTC.2018.8546373","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546373","url":null,"abstract":"Modern day electronics work in varied thermal conditions. The increase in demand of electronics, has led to miniaturization, use of plastic housing and more applications from the existing electronics in the market. The model for analysis consists of multi-layered Cu-FR4 Printed Circuit Board (PCB) with a power dissipation of 10 W (Volumetric distribution in PCB). The PCB is further enclosed in a housing. Representative internal air temperatures are estimated for evaluating thermal performance of housing in different studies. The dimensions of housings used for these studies are similar to that of typical automotive electronics. In the first study, an evaluation is carried out to understand the effect of orientation of metallic electronic housings w.r.t. incident airflow. Metallic housings are usually provided with heatsink and fins and the same are considered in our model. It is observed that the internal air temperature of the housing is minimum when the airflow is aligned in the direction of length of fins. It is also observed that an equally favorable orientation is when the airflow is directed on top of fins. Another study is done to evaluate the effect of orientation of metallic and plastic housings w.r.t. gravity in case of natural convection airflow. Unlike metallic housing, plastic housings are usually devoid of fins and heatsinks. For both metallic and plastic housings, it is observed that the internal air temperature is minimum when the plane of the housing is vertical. Moreover, for metallic housings best orientation is when fins are aligned vertically. In addition, a study to evaluate the effect of orientation of plastic housing w.r.t. incoming solar radiation in case of natural convection airflow is done. It is observed that internal air temperature is minimum when the plane of the housing is vertical. All these observations are made from steady state thermal simulations carried out using FloTHERMTM. The ambient is considered to be similar to any electronics mounted in an automotive. In addition, all the three modes of heat transfer i.e. conduction, convection and radiation are considered. This study will help forming guidelines for any design engineer, who wishes to choose an optimum orientation of housing, taking into account thermal performance of electronics.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124835268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Signal Integrity Transmission Line Using Microchip Capacitors and its Design Methodology","authors":"Shumpei Matsuoka, M. Yasunaga","doi":"10.1109/ESTC.2018.8546390","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546390","url":null,"abstract":"In the high-speed data transmissions in GHz domain,such as PCIe (Gen.5) and USB 5.0, slight impedance mismatching caused by via-holes and/or through-holes, or other small parasiticelements in the traces in printed circuit board (PCBs) causes serious deterioration of signal integrity (SI). And it is becoming next to impossible to ensure the SI by using the conventional impedance matching techniques as the frequency increases. In order toovercome this problem, we propose a novel high signal integrity transmission line structure called “Capacitor Segmental Transmission Line (C-STL)”. The C-STL is a novel signal integrity improving technique that makes use of not the characteristic impedance matching but the mismatching. In the C- STL, we use small microchip capacitors embedded in the PCB under the trace, and superpose the intentional reflections,which cause from the capacitors, onto the target distorted signal waves to restore them to ideal waveforms. In this paper, we also propose the design methodology of the C-STL and demonstrate its effectiveness using simulations and prototype measurements.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125048848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigations of BGA components’balls remanufacturing techniques for Circular Economy applications","authors":"J. Sitek, M. Kościelski, A. Arazna, K. Janeczek, W. Stęplewski","doi":"10.1109/ESTC.2018.8546357","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546357","url":null,"abstract":"This article presents the results of research aimed to evaluate the feasibility of automatic remanufacturing of BGA components balls using different techniques. It was presented possibility of component’s balls process optimization for each technique using the Genichi Taguchi method of experiments planning. The quality and parameters of BGA components balls were assessed by measurements using digital microscope as well as cross-sections. It was stated that all three investigated techniques are suitable for BGA components’ balls remanufacturing. The shape and size of balls were compared with catalog information for investigated components. Based on the results of investigation the recommendations for remanufacturing process of BGA component's balls were created.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125090309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Heterogeneous Integration of Vertical GaN Power Transistor on Si Capacitor for DC-DC Converters","authors":"Zechun Yu, S. Zeltner, N. Boettcher, G. Rattmann, J. Leib, C. F. Bayer, A. Schletz, T. Erlbacher, L. Frey","doi":"10.1109/ESTC.2018.8546362","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546362","url":null,"abstract":"Point of load (PoL) converters are emerging as common solution for industrial applications, telecommunications, server, and aerospace. In this work, a topology is designed for a single stage 48 V to 1 V PoL converter by using new gallium nitride (GaN) devices and integrated silicon capacitors. Various wafer-level packaging concepts such as die-to-wafer bonding, wafer-level thinning, and through-silicon via (TSV) will be presented and discussed based on this topology. Furthermore, two novel devices will be developed and used for the packaging concepts. One is a GaN transistor with vertical channel, which will exhibit significantly lower power losses when switching and converting power. The other is an integrated silicon capacitor with lateral geometry, in which positive and negative electrodes are insulated from the substrate and formed on the same side. Simulation is performed to compare the parasitic inductance from the different concepts. A direct bonding process is shown to provide flexibility in engineering new device geometries and can be exploited to mitigate the electrical parasitics.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123399442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Large-area femtosecond laser ablation of Silicon to create membrane with high performance CMOS-SOI RF functions","authors":"Arun Bhaskar, J. Philippe, M. Berthomé, E. Okada, J. Robillard, D. Gloria, C. Gaquière, E. Dubois","doi":"10.1109/ESTC.2018.8546407","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546407","url":null,"abstract":"Femtosecond laser processing is a tool of increasing relevance for controlled etching of metals, semiconductors, and dielectrics with minimum collateral damage. We make use of this technique to remove silicon locally from the handler substrate of Silicon-on-Insulator (SOI) dies. By combining laser removal with XeF2 etching, we create thin membranes of SP9T switch, with the handler silicon completely removed underneath. This is done in order to mitigate the losses and non-linear products caused by capacitive coupling to the handler substrate. We demonstrate the improvement of linearity and insertion loss of a switch (Fig. 9 and Fig. 10) by employing the proposed method. This could be of potential interest for future wireless applications like 5G.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121152722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermosonic-Adhesive (TS-A) Integration of Flexible Integrated Circuits on Flexible Plastic Substrates","authors":"G. Dou, A. Holmes, B. Cobb, S. Devenport, A. Jeziorska-Chapman, Jake Meeth, R. Price","doi":"10.1109/ESTC.2018.8546458","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546458","url":null,"abstract":"The integration of flexible integrated circuits (FlexICs) on flexible plastic substrates to deliver smart flexible electronic solutions has enormous potential across a range of consumer markets, including wearable devices, healthcare devices and smart labels. At present, reliable FlexIC integration for hybrid flexible electronic circuits is mainly based on conductive adhesive packaging which is too slow and/or expensive to address the highest volume products envisioned for consumer markets. In this research we have investigated low-cost bonding processes for FlexICs based on non-conductive adhesive (NCA) and thermosonic-adhesive (TS-A) bonding. Four-wire resistance tests, shear tests and bending tests were used for evaluation during process development. The results confirmed that NCA and TS-A bonding were feasible for FlexIC packaging, and the evaluation tests showed encouraging electrical and mechanical performance. This research is bringing novel bonding techniques that will significantly advance the development of low-cost manufacturing of smart flexible electronics to drive mass market adoption in consumer markets.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122921181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Morphology Variations of Primary Cu6Sn5 Intermetallics in Lead-Free Solder Balls","authors":"Maik Mueller, I. Panchenko, S. Wiese, K. Wolter","doi":"10.1109/ESTC.2018.8546391","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546391","url":null,"abstract":"This study focuses on the morphologies of primary Cu6Sn5 intermetallics in small free standing SnCu (Ø 270 μm) solder balls. Those showed a large variety of different shapes and sizes ranging from facetted hexagonal rods, to partly facetted splitting crystals and parallel growing branches, to dendritic crystals without facets. The results of electron backscatter diffraction (EBSD) measurements confirm [0001] as the major growth direction and the {10I0} planes as facets of the hexagonal rods. The formation of splitting crystals parallel to the {10I0} planes may be caused by a slight deviation of the major growth direction towards <2II0>. Morphology transition to dendritic structures can be influenced primarily by increasing the Cu content of the alloy and the cooling rate. However, strong variations occur even if the composition and the cooling rate are constant. Differences in undercooling of the Cu6Sn5 phase have been discussed as a possible reason, since a decreasing solidification temperature promotes a faster initial phase growth due to the increasing oversaturation of the melt’s Cu content.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125645920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal stability of high temperature Pb-free solder interconnect characterised by in-situ electron microscopy","authors":"Zhaoxia Zhou, Li Liu, Changqing Liu","doi":"10.1109/ESTC.2018.8546440","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546440","url":null,"abstract":"The present investigation aimed to use in-situ heating experiment in a transmission electron microscope (TEM) to live characterize the thermal stability of a Cu/Ni-W-P interlayer/ZnAl solder interconnect. It demonstrated the TEM was able to detect live intermetallic compounds (IMCs) growth during heating. In addition, stress building up was evidenced by the progressive evolving of the dislocations at the interface between NiW-P interlayer and the ZnAl Solder. However, due to the μm to nm scale of specimens’ dimensions required for electron microscopy, the sample preparation and data interpretation remains a challenge.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134640127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}