2018 7th Electronic System-Integration Technology Conference (ESTC)最新文献

{"title":"Controlling BGA joint microstructures using seed crystals","authors":"Z.L. Ma, S. Belyakov, J. Xian, T. Nishimura, K. Sweatman, C. Gourlay","doi":"10.1109/ESTC.2018.8546436","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546436","url":null,"abstract":"This paper overviews methods to catalyse the nucleation of tin in BGA solder joints and explores the potential of engineering tin nucleation to control joint microstructures. A range of heterogeneous nucleants for Sn is overviewed. It is shown that CoSn3, PtSn4, PdSn4 and IrSn4 can all catalyse Sn nucleation and substantially reduce the nucleation undercooling. The nucleation mechanisms are discussed in terms of a crystallographic lattice matching analysis, where each nucleant is shown to have good planar matching across the closest packed planes in each crystal structure. We then demonstrate an approach to incorporate the nucleants into solder joints as seed crystals to control the orientation of the tin nucleation event. With this approach, it is possible to generate single-crystal joints all with the same c-axis orientation.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129872421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Organic packaging with integrated NFC for harsh environments","authors":"Sven Johannsen, E. Bihler, M. Hauer","doi":"10.1109/ESTC.2018.8546424","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546424","url":null,"abstract":"Liquid Crystal Polymer (LCP), a thermoplastic dielectric material with superior material properties can be used both as the substrate material and as the encapsulation for small miniaturized electronic packages and modules. Very small form factors can be obtained by integrating the NFC coil into the LCP substrate. Encapsulation in LCP can provide hermetically sealed and chemically inert miniaturized electronic modules for sensors applications in medical, industrial and automotive markets.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"369 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120869384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The SiP Company [Advertisement]","authors":"","doi":"10.1109/estc.2018.8546439","DOIUrl":"https://doi.org/10.1109/estc.2018.8546439","url":null,"abstract":"","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121294887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influences of SMD Package and Substrate Warpage on Quality and Reliability –Measurement, Effects and Counteractions","authors":"H. Wohlrabe, K. Meier, Oliver Albrecht","doi":"10.1109/ESTC.2018.8546438","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546438","url":null,"abstract":"The coplanarity difference between a substrate or printed circuit board and a SMD package is a very important characteristic. It depends on the warpage of package and substrate and is caused by their heterogeneous build up. The materials involved – namely polymers, metals, ceramics etc. – come with differing coefficients of thermal expansion. This leads to temperature depending deformations due to thermal loads during assembly or field use. These warpage called deformations appear as twist and bow. A significant coplanarity or warpage mismatch can lead to quality issues during manufacturing. Solder joint shorts, pad cratering and open solder joints like head-inpillow or pin-in-pillow are examples of typical failure types. Also, additional mechanical stress especially in z-direction may occur in the solder joints and cause early failure under use.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121446273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Density Interconnect Processes for Panel Level Packaging","authors":"A. Ostmann, F. Schein, M. Dietterle, Marc Kunz, K. Lang","doi":"10.1109/ESTC.2018.8546431","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546431","url":null,"abstract":"Advanced packaging technologies like wafer-level fan-out and 3D System-in-Package (3D SIP) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for 3D SIPs with chips embedded into an organic laminate matrix. At first 6x6 mm2 chips with Cu bumps $( 100 mu mathrm{m}$ pitch) are placed into holes of a PCB core layer with low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the small gap down to $15 mu mathrm{m}$ between chips and core. The core provides fiducials for a local alignment of following processes, limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305x256 mm2 panel format, aiming for a final size of 600x600 mm2. On the top side of embedded chips $mathrm{a}25 mu mathrm{m}$ dielectric film is applied and the bump surface is exposed by plasma etching. By sputtering and electroplating of Cu contacts to the chips are formed without via opening. High aspect ratio vias around the chip to lower interconnect layers are formed by UV laser drilling. At via diameters of $17 mu mathrm{ma}$ drill hole depth of $74 mu mathrm{m}$ was achieved (aspect ration 4.4:1). Currently a microvia filling by Cu plating using a newly developed electrolyte could be demonstrated for aspect ratios up to 2.5:1. Then in $mathrm{a}7 mu mathrm{m}$ dry film photo resist forming of $4 mu mathrm{m}$ RDL structures was demonstrated by a newly developed Laser Direct Imaging (LDI) machine.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121515518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Board Level Reliability assessment of Wafer Level Chip Scale Packages for SACQ, a lead-free solder with a novel life prediction model","authors":"B. Muthuraman, B. Cañete","doi":"10.1109/ESTC.2018.8546504","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546504","url":null,"abstract":"Smart devices nowadays require more functionality in the integrated circuits with smaller packages. Wafer Level Chip Scale Package (WLCSP) is one of a best choice in the industry due to their small size and functionalitz. However, the reliability of such WLCSPs is very critical as they are used in consumer products. With new solder alloy material, SACQ (Sn92.45% / Ag4% / Cu 0.5% / Ni 0.05% / Bi 3%), it is vital to have a reliable life prediction mode for the Wafer Level Chip Scale package family. At the current industry trend, there is no much reliability assessment of WLCSPs using this new solder alloy. Even, if some exists, the accuracy between the board level reliability qualification test and numerical simulation is still more than 10% tolerance. In this work, a fatigue model is developed for SACQ for wafer level package family with the help of board level reliability qualification test; statistical approach and numerical approach using Finite Element Method (FEM) leading to a close correlation between the measured characteristic life time from temperature cycling on board (TCoB) tests and predicted life from numerical method. In this paper, a fatigue life prediction model for SACQ is introduced after studying five different wafer-level chip scale packages (WLCSP) subjected to Board Level Reliability (BLR) Temperature Cycling Qualification Tests (TCT). Number of solder interconnects (IOs) or pincounts in the wafer level packages ranges from 182 IOs till 360IOs. Temperature cycling range between - 40°C till +85°C is applied to samples, until significant solder joint fatigue failures are observed. A Weibull lifetime model is used to describe the BLR qualification test data. In order to validate BLR-TCT qualification, several numerical simulations are carried out based on Finite Element Method (FEM). Anand viscoplasticity material constitutive law is used for SACQ. Increment of volume averaged inelastic strain energy density is used as damage parameter in order to determine the fatigue life prediction model. This new fatigue life prediction model developed demonstrates that the relative error of the predicted life time for the wafer level chip scale package (WLCSPs) with the new lead-free solder is within relative error of 10% with respect BLR-TCT tests. Such a close correlation between measurement and numerical simulation for SACQ solder is illustrated first time in industry for WLCSP package family. This research work can answer the reliability challenges faced in WLCSP packages with SACQ as solder material and the future work will be based on impact of underfills on WLCSP device reliability with SACQ as solder material.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122523740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Miniaturized Printed Wiring Board Consisting of Polyimide Layers and Three Embedded Integrated Circuit Chips in Stacked Configuration","authors":"S. Sato, Koji Munakata, Masakazu Sato, N. Ueta, Yoshio Nakao, O. Nakao","doi":"10.1109/ESTC.2018.8546444","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546444","url":null,"abstract":"In the history of electronics packaging, continuous efforts have been made to achieve seemingly conflicting goals of reducing the size of electronic devices and increasing theirfunctionality. With more sophisticated packages, wearable and portable devices in particular are required to be more compact as well as reliable. To reduce the size of a package, embeddingIC (integrated circuit) chips inside is an effective solution instead of placing them on the surface. Based on this thought, we have developed a technology to produce WABE package}}$^{mathbf{TM}}$(wafer and board level device embedded package). The packages are produced by combining thin polyimide film layers and backgrinded IC chips. WABE Package technology has an unmatched feature thatit can reduce the footprint of a package drastically by stacking IC chips if multiple chips need to be embedded in the package. Even if the package has two or morechips, the increase in the thickness of the chip-stack structure is very limited because each layer is so thin. Another feature of the technology is parallel fabrication of each polyimide-based layer with vias filled with a conductive material for interconnection. The individual and simultaneous preparation of layers enables “one-step” colamination, which has an advantagethat only one-time press is needed even though the number of layers increases due to the chip-stack structure. This report describes the fabrication of aprototype circuit board that consists of 14 copper layers and 3 IC chips embedded vertically in them. The board is less than 0.9 mm in thickness even though it includes a large number of layers. We also report the results of various reliability testing conducted on the package. These results were obtained by electrical measurements of daisy chain patterns formed between some of the layers. The prototype showed high reliability under moisture and heat test conditions simulating those in autoclave sterilization and heat-shock test conditions simulating those in the production process. These results show that the WABE Package technology that allows three chips to be embedded vertically in the package is the most promising packaging technology for extremely miniaturizing electronic circuits for medical and wearable electronics.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123293999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Precision Numerical and Experimental Thermal Studies of Microelectronic Packages in Still Air Chamber Tests","authors":"P. M. Souare, M. K. Touré, Stéphanie Allard, B. Borzou, J. Sylvestre, B. Foisy, É. Duchesne","doi":"10.1109/ESTC.2018.8546346","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546346","url":null,"abstract":"In order to contribute to a better understanding of the relevant thermal phenomena, we have performed a high precision comparison of a microelectronic package cooled by natural convection with experimental data obtained in the Still Air JEDEC configuration. The heat transfer problem was solved by a bidirectional coupling method iterating between the solid domain and the fluid domain. At the first iteration, the conduction heat transfer in the solid domain was solved using convection coefficients estimated from empirical relations available from the literature, for each solid-fluid interface. The numerical temperature field so-obtained at the solid-fluid interface was then applied as a boundary condition for the numerical simulation of the of air flow around the package by computational fluid dynamics (CFD), to find the velocity, pressure and temperature fields in the fluid domain. The convection coefficient of each element at the solid-fluid interfaces was then computed from the heat flux in the CFD results. Finally, the convection coefficients obtained from the CFD analysis were applied back to the solid domain, and the same procedure was repeated iteratively until the solution converged to a stable temperature field. The comparison between the heat transfer coefficients obtained from the CFD method and those obtained from the empirical relations shows significant differences, thus validating the utility and effectiveness of the iterative approach to obtain precise thermal results. The numerical results for temperature were compared with measurements from a test vehicle. The experiments were carried out under natural convection according to the JEDEC standards in a still air chamber for the horizontal and vertical positioning of the test vehicle. The large difference in temperature between the walls of the still air chamber and the test vehicle leads to large errors in predicted temperatures if the radiation effects are not properly treated in the heat transfer problem. The junction temperatures obtained with the numerical simulations in the vertical and horizontal orientations were in excellent agreement with the experimental measurements, with an absolute difference of less than 1 °C. Such agreement demonstrates the accuracy of our methodology for the modeling of natural heat transfer for microelectronic packages mounted on printed circuit boards in the horizontal and vertical orientations.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115331254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TCB optimization for stacking large thinned dies with 40 and 20 μm pitch microbumps","authors":"C. Gerets, J. Derakhshandeh, P. Bex, M. Lofrano, V. Cherman, T. Cochet, K. Rebibis, G. Beyer, Andy Miller, E. Beyne","doi":"10.1109/ESTC.2018.8546425","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546425","url":null,"abstract":"In this paper optimization process of D2W (Die to Wafer) TCB (Thermal Compression Bonding) stacking for thinned, warped and large dies are investigated. TCB related characteristics of WLUF (Wafer Level Underfill) is studied in detail by both analytical calculations/simulations and insitu deformation measurement techniques and then the results are used to lower the required bond force of TCB profile. Further optimizations include the enhancement of the interface temperature uniformity, and modification of the top bond tool called Thermode. These optimizations result in good flattening of the thin and warped large die, and uniform pressure distribution during the TCB process. The large stacked dies show very low warpage, very good joint formation between TSVs and 20um pitch microbumps and close to 100{%} electrical yield.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"377 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115851734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of environmental factors like temperature and humidity on MEMS packaging materials.","authors":"Mahesh Yalagach, P. Fuchs, I. Mitev, T. Antretter, M. Feuchter, A. Wolfberger, Tao Qi","doi":"10.1109/ESTC.2018.8546484","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546484","url":null,"abstract":"Microelectromechanical systems (MEMS) and MEMS packaging solutions are gaining increased interests for electronic applications. These packages feature a variety of polymeric materials and composites e.g. fiber reinforced polymer laminates, insulating and conductive adhesives. Due to the sensitivity of MEMS devices to mechanical stress and environmental factors such as temperature and humidity, the influence of these factors on the device’s performance needs to be accounted for. In this contribution, a fabric woven glass fiber reinforced epoxy resin (BT epoxy resin) and two chosen adhesives commonly used in semiconductor and MEMS packaging have been considered and their dependency on environmental parameters have been studied with different testing methods. Based on the measured material properties a simulation process predicting the package under defined environmental loads is presented.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130746348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}