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IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006最新文献

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Average current reduction in (W)CDMA power amplifiers (W)CDMA功率放大器的平均电流减小
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651171
D. Teeter, E. Spears, H.D. Bui, H. Jiang, D. Widay
{"title":"Average current reduction in (W)CDMA power amplifiers","authors":"D. Teeter, E. Spears, H.D. Bui, H. Jiang, D. Widay","doi":"10.1109/RFIC.2006.1651171","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651171","url":null,"abstract":"Statistical average current consumption of conventional CDMA and WCDMA [(W)CDMA] power amplifiers is compared to that obtained by using DC-DC converters, analog bias control, and low power efficiency enhancement (LPEE) techniques. A discussion of theoretical limits, strengths, and weaknesses for each approach is presented","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122281848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A fully integrated 2.4-GHz CMOS RF transceiver for IEEE 802.15.4 一个完全集成的2.4 ghz CMOS射频收发器，用于IEEE 802.15.4
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651136
I. Kwon, Y. Eo, S. Song, Kyudon Choi, Heungbae Lee, Kwyro Lee
{"title":"A fully integrated 2.4-GHz CMOS RF transceiver for IEEE 802.15.4","authors":"I. Kwon, Y. Eo, S. Song, Kyudon Choi, Heungbae Lee, Kwyro Lee","doi":"10.1109/RFIC.2006.1651136","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651136","url":null,"abstract":"A fully integrated 2.4 GHz CMOS transceiver IC for the low power wireless personal area network (WPAN) is reported. This is based on a dual-conversion architecture receiver and transmitter which are suitable for silicon integration. The frequency synthesizer offering 1.92 GHz and 480 MHz quadrature LO signals are also integrated on the radio chip. In the proposed transceiver, linearity is improved by using current mirror amplifier based mixer. The optimization between dynamic range and current consumption has been achieved by the interleaved analog filter-amplifier chain. The fully integrated transceiver is fabricated in 0.18 mum CMOS technology and the die area of the single-chip IC is 3.7 mm times 3.6 mm. It consumes only 31 mW in the receiver mode and 42 mW in the transmitter mode with 1.8-V supply","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126946532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
1 to 20 GHz CMOS distributed mixer using asymmetric coplanar strip transmission lines 采用非对称共面带状传输线的1至20 GHz CMOS分布式混频器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651130
N. Garg, L. B. Lok, I. Robertson, M. Chongcheawchamnan, A. Worapishet
{"title":"1 to 20 GHz CMOS distributed mixer using asymmetric coplanar strip transmission lines","authors":"N. Garg, L. B. Lok, I. Robertson, M. Chongcheawchamnan, A. Worapishet","doi":"10.1109/RFIC.2006.1651130","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651130","url":null,"abstract":"The design and measured performance of a 1 to 20 GHz CMOS distributed mixer is presented. The design is realized in a standard 0.25mum process and uses asymmetric coplanar strip (CPS) transmission line interconnects for low loss and small circuit size. The measured response shows conversion gain of 1dB with 7dBm LO power and input return loss better than 12dB up to 20 GHz","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125719785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Millimeter-wave wireless personal area network systems 毫米波无线个人区域网络系统
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651160
H. Ogawa
{"title":"Millimeter-wave wireless personal area network systems","authors":"H. Ogawa","doi":"10.1109/RFIC.2006.1651160","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651160","url":null,"abstract":"A millimeter-wave wireless personal network (WPAN) system is designed to provide short-range, high-speed multi-media data services to terminals in rooms or office space. Millimeter-wave ad-hoc wireless access system has been developed by the Yokosuka Research Park (YRP) collaborated group which was organized by NICT Yokosuka Radio Communication Research Center. This system is designed to provide easy connectivity, network flexibility and high transmission data rate suitable for WAPN service. The millimeter-wave ad-hoc system and its technologies, and the other 60-GHz applications are first presented, the millimeter-wave interest (mmWIG), study (SG3c) and task (TG3c) groups which were recently organized and approved within IEEE802.15 are introduced and its activity are presented","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130433876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
1-11 GHz ultra-wideband resistive ring mixer in 0.18-/spl mu/m CMOS technology 1-11 GHz超宽带电阻环形混频器，采用0.18-/spl mu/m CMOS技术
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651178
T. Chang, J. Lin
{"title":"1-11 GHz ultra-wideband resistive ring mixer in 0.18-/spl mu/m CMOS technology","authors":"T. Chang, J. Lin","doi":"10.1109/RFIC.2006.1651178","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651178","url":null,"abstract":"In this paper, an ultra-wideband down-conversion resistive ring mixer is designed using the mixed-mode TSMC CMOS 0.18-mum technology. This mixer down-converts RF signals in the range of 1-11 GHz to fixed IF of 500MHz using LO signals at 500MHz higher than the corresponding RF frequencies. The conversion loss within this band is 7plusmn0.5dB. The input 1dB compression point (P1dB) for the entire band is about 5dBm, and the input third order interception point (IIP3) is about 10dBm. The LO power required to obtain lowest conversion loss for this resistive mixer is 9dBm. The mixer core has no power consumption whereas the IF output buffer consumes 3mW. This mixer can be used in high dynamic range low-power ultra-wideband communication systems","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"296 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134302104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Novel 3 port characterisation and de-embedding for high performance on-silicon K/sub a/ band balun 新颖的3端口表征和去嵌入高性能硅上K/sub /波段平衡器
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651135
J. O' Sullivan, K. McCarthy, P. Murphy
{"title":"Novel 3 port characterisation and de-embedding for high performance on-silicon K/sub a/ band balun","authors":"J. O' Sullivan, K. McCarthy, P. Murphy","doi":"10.1109/RFIC.2006.1651135","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651135","url":null,"abstract":"A 3 port de-embedding technique is presented. The method is used to accurately characterise the performance of an on-silicon multilayer balun. Three de-embedding structures have been fabricated along with the balun itself. From 25 to 40 GHz the de-embedded balun achieves phase and magnitude imbalances of less than 5 degrees and 1 dB, respectively. Excellent correspondence between the measured balun parameters and EM simulation results is observed after de-embedding is applied","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133192559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A CMOS 3.1-10.6 GHz UWB LNA employing stagger-compensated series peaking 采用交错补偿串联峰值的CMOS 3.1-10.6 GHz超宽带LNA
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651088
S. Shekhar, X. Li, D. Allstot
{"title":"A CMOS 3.1-10.6 GHz UWB LNA employing stagger-compensated series peaking","authors":"S. Shekhar, X. Li, D. Allstot","doi":"10.1109/RFIC.2006.1651088","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651088","url":null,"abstract":"A fully-integrated common-gate UWB LNA employs a stagger-compensated series peaking technique to extend bandwidth, and a capacitor cross-coupled gm-boosting technique to reduce NF and power. A simple input matching scheme obviates the use of multiple inductors and complex filters. For two versions in 0.18 mum CMOS, BW extension factors are 4.1times and 4.9times, -3dB bandwidths are 1.3-10.7 GHz and 1.3-12.3 GHz, NF are 4.4 dB and 4.6 dB, peak S21 are 8.5 dB and 8.2 dB, and peak IIP3 are 8.3 dBm and 9.1 dBm, respectively. Each differential LNA draws 2.5 mA from 1.8 V","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129158249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
A compact high rejection 2.4 GHz WLAN front-end module enables multi-radio co-existence up to 2.17 GHz 紧凑的2.4 GHz高抑制WLAN前端模块可实现高达2.17 GHz的多无线电共存
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651099
C. Huang, W. Vaillancourt, A. Parolin, C. Zelley, Z. Gu
{"title":"A compact high rejection 2.4 GHz WLAN front-end module enables multi-radio co-existence up to 2.17 GHz","authors":"C. Huang, W. Vaillancourt, A. Parolin, C. Zelley, Z. Gu","doi":"10.1109/RFIC.2006.1651099","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651099","url":null,"abstract":"A compact 5 times 6 times 1.4 mm3 2.4 GHz wireless LAN front-end module (FEM) capable of supporting multi-radio co-existence up to 2.17 GHz is presented. The FEM features 28 dB gain, low current consumption of 120 mA for 15 dBm output power with < 3% EVM at 54Mbps transmissions, < -170 dBm/Hz noise emission up to 2.17 GHz, >45 dB receive path out-of-band rejection up to 2 GHz, and 3.5 dB insertion loss for receive path. The FEM also features >30 dB transmit/receive isolation under 10:1 mismatch at idle port, an integrated regulator, and a temperature compensated power detector. All these features provide an easy integration of a WLAN radio into multi-standard 33 and future generation handsets up to UMTS bands","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128761026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A +7.9dBm IIP3 LNA for CDMA2000 in a 90nm digital CMOS process 用于CDMA2000的+7.9dBm IIP3 LNA，采用90nm数字CMOS工艺
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651201
D. Griffith
{"title":"A +7.9dBm IIP3 LNA for CDMA2000 in a 90nm digital CMOS process","authors":"D. Griffith","doi":"10.1109/RFIC.2006.1651201","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651201","url":null,"abstract":"A highly linear low noise amplifier (LNA) has been implemented in a standard digital 90nm CMOS process. At 880MHz the amplifier provides a forward power gain (S21) of 14.5dB with a supply voltage of 1.4V and a current consumption of 8.3mA. The noise figure was measured to be 1.0dB and the input third order intercept point (IP3) is +7.9dBm. Two lower gain modes have also been implemented; one with a lower transconductance gain stage, and one with a bypass switch. These performance parameters make the amplifier suited for the CDMA2000 cellular standard","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129134764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A transformer based 1.8-1.9GHz low-IF receiver for 1V in 0.13/spl mu/m CMOS 基于变压器的1.8-1.9GHz低中频接收器，用于0.13/spl mu/m CMOS
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 Pub Date : 2006-06-11 DOI: 10.1109/RFIC.2006.1651150
C. Hermann, C. Miinker, H. Klar
{"title":"A transformer based 1.8-1.9GHz low-IF receiver for 1V in 0.13/spl mu/m CMOS","authors":"C. Hermann, C. Miinker, H. Klar","doi":"10.1109/RFIC.2006.1651150","DOIUrl":"https://doi.org/10.1109/RFIC.2006.1651150","url":null,"abstract":"A fully integrated low-IF receiver for 1.8-1.9GHz has been realized in 0.13mum CMOS. The receiver consists of a VCO, an IQ-divider, an LNA, and a double balanced IQ-mixer. The RF input stage and the commutating stage of the IQ-mixer are current coupled via an on-chip transformer which is operating in resonant mode and is performing a current gain. A design method is presented to reduce the input impedance of the mixer's commutating stage in order to improve the current gain of the on-chip transformer. This helps to improve the IIP3 and to reduce the power consumption. The receiver takes 25.7mA from a 1 V supply to give an IIP3 of -20.3dBm, an input referred 1-dB compression point of -30.7dBm, a conversion gain of 29.2dB and a SSB noise figure of 3.0dB","PeriodicalId":194071,"journal":{"name":"IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116985473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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