B. Pramanick, P. Kundu, T. K. Bhattacharyya, Soumen Das
{"title":"Design and fabrication of silicon membrane by wet bulk micromachining process","authors":"B. Pramanick, P. Kundu, T. K. Bhattacharyya, Soumen Das","doi":"10.1109/TECHSYM.2011.5783828","DOIUrl":"https://doi.org/10.1109/TECHSYM.2011.5783828","url":null,"abstract":"A silicon membrane is very important part of the MEMS (Micro-Electro-Mechanical System) devices or itself is a useful device. The design and simulation has been performed in COVENTORWARE® for the fabrication of membrane. The thickness of Piezoelectric actuator is assumed 9mm as this is the thickness of commercially available Lead Zirconate Titanate (PZT) actuator. Potassium Hydroxide (KOH) is used as etchant of silicon for the realisation of 75µm thick silicon membrane. The micromachining is carried out at 70°C using 44% KOH solution. The etch rate depends on the etchant concentration as well as temperature. The etch rate of silicon decreases with the increase of KOH concentration and increases with the increase of temperature. The membrane is designed and fabricated for high fluid pressure application of piezoelectric actuated devices.","PeriodicalId":193763,"journal":{"name":"IEEE Technology Students' Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124959374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Chanda, S. Kundu, I. Adak, A. Dandapat, H. Rahaman
{"title":"Design and analysis of tree-multiplier using single-clocked energy efficient adiabatic Logic","authors":"M. Chanda, S. Kundu, I. Adak, A. Dandapat, H. Rahaman","doi":"10.1109/TECHSYM.2011.5783851","DOIUrl":"https://doi.org/10.1109/TECHSYM.2011.5783851","url":null,"abstract":"In this paper ultra low power characteristics of the newly proposed energy efficient adiabatic Logic (EEAL) is investigated. EEAL is based on differential cascode voltage swing (DCVS) logic, uses only a single sinusoidal source as supply-clock. With minimal clocking overhead this proposed logic eliminates the floating output problem and enhances the energy efficiency significantly. An EEAL based 8×8 tree multiplier by 4-2 compressor circuits have been implemented in a TSMC 0.18 µm CMOS technology. CADENCE simulation shows that EEAL based multiplier circuit consumes only 25%–30% of total energy consumed by single clocked adiabatic logics. Both simulation and measurement results verify the functionality of such logic, making it suitable for implementing energy-aware and performance-efficient sequential circuit.","PeriodicalId":193763,"journal":{"name":"IEEE Technology Students' Symposium","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126333489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Saptarshi Das, S. Mukherjee, Indranil Pan, Amitava Gupta, S. Das
{"title":"Identification of the core temperature in a fractional order noisy environment for thermal feedback in nuclear reactors","authors":"Saptarshi Das, S. Mukherjee, Indranil Pan, Amitava Gupta, S. Das","doi":"10.1109/TECHSYM.2011.5783821","DOIUrl":"https://doi.org/10.1109/TECHSYM.2011.5783821","url":null,"abstract":"In this paper, the core temperature of a 540 MWe Pressurized Heavy Water Reactor (PHWR) has been estimated from the measured temperature of the coolant using system identification techniques. The formulation is done considering fractional order (FO) dynamics for the sensor noise (i.e. 1/ƒα noise) and the conventional white noise in measurement. Performance study with different least square based linear estimators and nonlinear AutoRegressive eXogenous (ARX) and nonlinear Hammerstein-Wiener class of estimators for system identification has been done to show their relative merits to handle fractional order noise dynamics for estimating reactor core temperature.","PeriodicalId":193763,"journal":{"name":"IEEE Technology Students' Symposium","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122841043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Paul, Amaresh Pothnal, C. Mandal, B. Bhattacharya
{"title":"Design and implementation of packet filter firewall using Binary Decision Diagram","authors":"G. Paul, Amaresh Pothnal, C. Mandal, B. Bhattacharya","doi":"10.1109/TECHSYM.2011.5783856","DOIUrl":"https://doi.org/10.1109/TECHSYM.2011.5783856","url":null,"abstract":"Packet filtering is the one of the major contemporary firewall design techniques. An important design goal is to arrive at the decision at the packet only. Implementation of such packet filter using Binary Decision Diagram (BDD) gives more advantages in terms of memory usage and look up time. In the case of the list-based packet filter firewall where rules are checked one by one for each incoming packet, the time taken to decide on a packet is proportional to the number of rules. The performance is improved with rule promotion but that itself a slow procedure. In this work we present a BDD-based approach which gives much better result in terms of number of comparisons or accesses the rule list make. Results on 1 million packets show that for most-accept packets, on an average, 75% reduction happens in such comparisons when BDD-based approach is used over list-based with promotion approach. For most-reject packets this reduction is nearly 34%.","PeriodicalId":193763,"journal":{"name":"IEEE Technology Students' Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128567868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Saha, A. Banerjee, P. Bhattacharyya, A. Dandapat
{"title":"High speed ASIC design of complex multiplier using Vedic Mathematics","authors":"P. Saha, A. Banerjee, P. Bhattacharyya, A. Dandapat","doi":"10.1109/TECHSYM.2011.5783852","DOIUrl":"https://doi.org/10.1109/TECHSYM.2011.5783852","url":null,"abstract":"Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 Sutras (Formulae). A high speed complex multiplier design (ASIC) using Vedic Mathematics is presented in this paper. The idea for designing the multiplier and adder/sub-tractor unit is adopted from ancient Indian mathematics “Vedas”. On account of those formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay in comparison with DA based architecture and parallel adder based implementation which are most commonly used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using standard 90nm CMOS technology. The propagation delay of the resulting (16, 16)×(16, 16) complex multiplier is only 4ns and consume 6.5 mW power. We achieved almost 25% improvement in speed from earlier reported complex multipliers, e.g. parallel adder and DA based architectures.","PeriodicalId":193763,"journal":{"name":"IEEE Technology Students' Symposium","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126195283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Estimation of QPSK signal via different smart array antennas deploying gradient approach","authors":"K. Subhashini, S. Jagarlamudi, G. Lalitha","doi":"10.1109/TECHSYM.2011.5783809","DOIUrl":"https://doi.org/10.1109/TECHSYM.2011.5783809","url":null,"abstract":"Smart Antenna systems have recently received increasing interest as the demand for better quality and new value added services on the existing wireless communication systems. These system of antennas include different array geometry and different adaptive techniques to enhance the received modulated signal with a fixed DOA by suppressing the inferences. Although enormous study has been done on smart antennas, special emphasis has not been provided to the antenna array structure. In this paper the performance of smart antenna in terms of the received signal for linear, circular and planararrays is observed. The adaptive array structure for all the geometry's is trained using modified LMS algorithm and RLS algorithm. Comparison is made for different array structures using both the adaptive techniques.","PeriodicalId":193763,"journal":{"name":"IEEE Technology Students' Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127354928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Compact CPW-fed antenna for wideband application","authors":"I. Balakrishna, R. Malmathanraj, S. Raghavan","doi":"10.1109/TECHSYM.2011.5783811","DOIUrl":"https://doi.org/10.1109/TECHSYM.2011.5783811","url":null,"abstract":"This paper presents a CPW-fed antenna for wideband application. This Antenna satisfies the licensed frequency band of WLAN (5.15–5.85)GHz and X-Band(8–12)GHz application. A resonant frequency for WLAN at 5.57GHz and 11.27GHz for h=1mm having return loss lower than −10dB. This antenna is designed on a substrate with dielectric constant εr=4.4. With a size 15.2mm×15.6mm×1mm the antenna operates for wideband application. The effects of shape, length, size, and location of feeding point, substrate and their thickness have been evaluated. And obtained 2D radiation patterns with elevation, VSWR, Return loss, gain and antenna efficiency. The simulation results of this antenna are analyzed by using Method of Moment (MoM) from IE3D software.","PeriodicalId":193763,"journal":{"name":"IEEE Technology Students' Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131455176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Characterisation of bulk GaSb using TCAD","authors":"F. Ali, Priyabrata Pattanaik, S. K. Kamilla","doi":"10.1109/TECHSYM.2011.5783847","DOIUrl":"https://doi.org/10.1109/TECHSYM.2011.5783847","url":null,"abstract":"The III–V compounds have turned out to be promising candidates for high speed electronics and photonic devices. Among III–V compounds, gallium antimonide (GaSb) is particularly interesting as a substrate material because its lattice parameter matches solid solutions of various ternary and quaternary III–V compounds whose band gaps cover a wide spectral range. These have stimulated a lot of interest in GaSb for basic research in materials as well as device fabrication. In this paper, investigation is done for the hole transport property of bulk GaSb with intrinsic concentration 1.5×1015 cm−3. Hole concentration and mobility of bulk GaSb were investigated by simulation method using the device simulation software ATLAS (SILVACO) in the temperature range from 77K to 320K in an interval of 5Kand 10K. It also shows that the effective hole mobility is about 461 cm2/Vs with the concentration ≈ 1.5 × 1015 cm−3 at room temperature i.e. 300K. It has been found that the effective mobility is affected by ionized impurity scattering; in contrast at higher temperatures (≈ 300K) acoustic, polar optical and non-polar optical scattering processes dominate the mobility. The agreement of simulated data with that of reported experimental data is found to be satisfactory.","PeriodicalId":193763,"journal":{"name":"IEEE Technology Students' Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123368352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Data logging and supervisory control of process using LabVIEW","authors":"Subhransu Padhee, Y. Singh","doi":"10.1109/TECHSYM.2011.5783838","DOIUrl":"https://doi.org/10.1109/TECHSYM.2011.5783838","url":null,"abstract":"This paper gives an overview of data acquisition, data logging and supervisory control system of a plant consisting of multiple boilers. Data acquisition, data logging and supervisory control are the basic building blocks of plant automation. This paper takes a case study of plant consisting of multiple boilers where multiple process variables of the boilers need to be acquired from the field and monitored. The data of the process variables needs to be logged in a database for further analysis and supervisory control. A LabVIEW based data logging and supervisory control program simulates the process and the generated data are logged in to the database with proper indication about the status of the process variable.","PeriodicalId":193763,"journal":{"name":"IEEE Technology Students' Symposium","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132275237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mixedmode circuit simulation of silicon and germanium nanowire MOSFETs - A comparative study","authors":"G. Mahajan, V. Chaubey, R. Narang, M. Saxena","doi":"10.1109/TECHSYM.2011.5783832","DOIUrl":"https://doi.org/10.1109/TECHSYM.2011.5783832","url":null,"abstract":"Nanowire MOSFETs have been recognized as one of the possible choices to continue the scaling of CMOS beyond conventional scaling limits. In present study we study various aspects of device characteristics and Mixedmode circuit behavior of Silicon and Germanium Nanowire MOSFETs. The various parameters determining the behavior of device in the analog/digital circuits is studied and compared for Nanowire MOSFET with Si and Ge as channel material. Important parameters such as transconductance, output conductance, Ion/Ioff ratio and short channel parameters have been extracted and compared for Silicon and Germanium. The Mixed mode circuit simulation has been done for Inverter (VTC and transient analysis) and 3 stage Ring Oscillator (transient analysis). Results of these simulations give insights into the in-circuit behavior of these future generation devices.","PeriodicalId":193763,"journal":{"name":"IEEE Technology Students' Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129790178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}