Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems最新文献

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Design of chaotic binary sequences with good statistical properties based on piecewise linear into maps 基于分段线性映射的统计性能良好的混沌二值序列设计
A. Tsuneda, K. Eguchi, T. Inoue
{"title":"Design of chaotic binary sequences with good statistical properties based on piecewise linear into maps","authors":"A. Tsuneda, K. Eguchi, T. Inoue","doi":"10.1109/MN.1999.758873","DOIUrl":"https://doi.org/10.1109/MN.1999.758873","url":null,"abstract":"This paper shows design of chaotic binary sequences with good statistical properties based on one-dimensional piecewise linear maps. Such chaotic binary sequences are shown to be balanced and i.i.d. (independent and identically distributed). We also realize such sequences by an analog circuit using switched-current (SI) techniques. The statistical properties of the sequences generated by such an analog circuit are also investigated by SPICE simulations.","PeriodicalId":191273,"journal":{"name":"Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127213203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Design and prototyping of a MEMS-oriented distributed feed-back processor 面向mems的分布式反馈处理器的设计与原型
Y. Mita, A. Kaiser, P. Garda, M. Milgram, H. Fujita
{"title":"Design and prototyping of a MEMS-oriented distributed feed-back processor","authors":"Y. Mita, A. Kaiser, P. Garda, M. Milgram, H. Fujita","doi":"10.1109/MN.1999.758866","DOIUrl":"https://doi.org/10.1109/MN.1999.758866","url":null,"abstract":"This paper presents a novel architecture of a distributed processor for sensor feedback control of a fully integrated MEMS (microelectromechanical systems). The architecture enables one to produce versatile processors with minimal number of transistors and wirings for communication. A micro conveyance system which conveys an object of different shape in different directions is adopted for demonstration. Prototyping using high capacity programmable logic devices (PLDs) and experiments with real images show that the architecture is perfectly suitable for distributed MEMS.","PeriodicalId":191273,"journal":{"name":"Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124953533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and evaluation of a reconfigurable digital architecture for self-organizing maps 自组织地图的可重构数字架构设计与评价
B. Pino, F. Pelayo, J. Ortega, A. Prieto
{"title":"Design and evaluation of a reconfigurable digital architecture for self-organizing maps","authors":"B. Pino, F. Pelayo, J. Ortega, A. Prieto","doi":"10.1109/MN.1999.758892","DOIUrl":"https://doi.org/10.1109/MN.1999.758892","url":null,"abstract":"A digital SIMD architecture to implement Self-Organizing Maps is presented. Custom bit-serial processing elements have been designed not only to obtain a high integration density (an area of 0.06 mm/sup 2/ per PE is estimated for a 0.25 /spl mu/m process and a standard cell design) but also to improve flexibility. The dimensionality of the map, the topological neighbourhood and the kernel function shape are programmable. A modular approach allows several neurochips to be interconnected to expand both the number of neurons and the number of synapses per neuron, performing a mixed synapse/neuron parallelism. In a system composed of a fixed number of neurochips, the number of neurons and synapses physically implemented can be reconfigured in order to achieve the optimal exploitation of hardware resources. The performance of the proposed architecture for fully implemented networks and virtual nets has been evaluated. A significant speedup improvement is achieved in comparison with a similar architecture without synapse parallelism.","PeriodicalId":191273,"journal":{"name":"Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126087158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An analog local cluster neural net for a 3 V supply 模拟本地集群神经网络为一个3v电源
T. Korner, J. Sitte, U. Ruckert
{"title":"An analog local cluster neural net for a 3 V supply","authors":"T. Korner, J. Sitte, U. Ruckert","doi":"10.1109/MN.1999.758877","DOIUrl":"https://doi.org/10.1109/MN.1999.758877","url":null,"abstract":"The local cluster neural net (LC net) is a feedfoward net suitable for continuous function approximation and discrete classification tasks. All operations of the LC net can be realized in analog circuits. Therefore we implemented the LC net in analog VLSI hardware for a 3 V power supply. Main applications of the LC net are control tasks in autonomous systems that can be battery powered. In this paper we describe the CMOS VLSI realization and present the results of the comprehensive test measurement for characterising the performance of the implementation.","PeriodicalId":191273,"journal":{"name":"Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125259127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analog velocity sensing circuits based on bio-inspired correlation neural networks 基于仿生相关神经网络的模拟速度传感电路
M. Ohtani, T. Asai, H. Yonezu, N. Ohshima
{"title":"Analog velocity sensing circuits based on bio-inspired correlation neural networks","authors":"M. Ohtani, T. Asai, H. Yonezu, N. Ohshima","doi":"10.1109/MN.1999.758888","DOIUrl":"https://doi.org/10.1109/MN.1999.758888","url":null,"abstract":"We propose simple analog MOS circuits producing one-dimensional optical flows aiming at the realization of compact motion-sensing circuits. In the proposed circuit, the optical flow is computed by a number of local motion sensors, as in biological motion-sensing systems. Mimicking the structure of biological motion detectors made the circuit structure quite simple, compared with conventional velocity sensing circuits. Extensive simulation results using SPICE and experimental results indicated that the proposed circuits could compute local velocities of a moving light spot and showed direction selectivity for the moving spot, which implies that a high-resolution motion-sensing chip can be realized using standard analog very large-scale integration technology.","PeriodicalId":191273,"journal":{"name":"Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133496331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Systolic implementation of a pipelined on-line backpropagation 收缩实现的一个流水线在线反向传播
R. G. Gironés, A.M. Salcedo
{"title":"Systolic implementation of a pipelined on-line backpropagation","authors":"R. G. Gironés, A.M. Salcedo","doi":"10.1109/MN.1999.758891","DOIUrl":"https://doi.org/10.1109/MN.1999.758891","url":null,"abstract":"The paper describes the implementation of a systolic array for a multilayer perceptron with a hardware-friendly learning algorithm. A pipelined adaptation of the on-line backpropagation algorithm is shown. It better exploits the parallelism because both the forward and backward phases can be performed simultaneously. As a result, a combined systolic array structure is proposed for both phases. Analytic expressions show that the pipelined version is more efficient than the non-pipelined version. The design is simulated using VHDL at different levels of abstraction to solve three databases and the experimental results agree with analytical estimates. Furthermore, the speed of convergence, the generalization capability and the precision required for both versions are evaluated in order to discuss the neural network performance for the proposed variation-compared with the standard so-called online backpropagation algorithm.","PeriodicalId":191273,"journal":{"name":"Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133472025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
2D focal plane steerable and scalable cortical filters [image sensor] 二维焦平面可调可伸缩皮质滤光片[图像传感器]
Bertram E. Shi
{"title":"2D focal plane steerable and scalable cortical filters [image sensor]","authors":"Bertram E. Shi","doi":"10.1109/MN.1999.758869","DOIUrl":"https://doi.org/10.1109/MN.1999.758869","url":null,"abstract":"We describe a 25/spl times/25 pixel image sensor which spatially filters a set of input currents supplied by an array of phototransistors by two orientation selective image filters. The filters are similar to even and odd Gabor filters, which have been used to model the receptive fields of neurons in the visual cortex. The circuit architecture implementing the image filter consists of two resistive networks which are coupled by transconductance amplifiers. The tuned orientation can be steered and the filter response scaled by adjusting the conductances of the resistors and gains of the transconductance amplifiers. The architecture implemented here is a 2D extension of a previous 1D architecture with some modifications which enable one chip to implement filters of arbitrary orientation.","PeriodicalId":191273,"journal":{"name":"Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116846185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
The computational infrastructure for cellular visual microprocessors 细胞视觉微处理器的计算基础结构
P. Szolgay, Á. Zarándy, S. Zold, T. Roska, P. Foldesy, L. Kék, T. Kozek, K. László, I. Petrás, C. Rekeczky, I. Szatmári, D. Bálya
{"title":"The computational infrastructure for cellular visual microprocessors","authors":"P. Szolgay, Á. Zarándy, S. Zold, T. Roska, P. Foldesy, L. Kék, T. Kozek, K. László, I. Petrás, C. Rekeczky, I. Szatmári, D. Bálya","doi":"10.1109/MN.1999.758846","DOIUrl":"https://doi.org/10.1109/MN.1999.758846","url":null,"abstract":"A new computational paradigm is emerging for spatio-temporal problems: analogic CNN array-computing. The elementary instructions and programming techniques, however, are drastically different from any other computers. These elementary instructions represent complex, spatio-temporal, nonlinear, dynamic phenomena including all the standard and exotic properties of simple image processing operators as well as waves, patterns, and \"evolving systems\". Meanwhile, a computational infrastructure has also emerged interfacing this revolutionary computing technology to digital systems as well as enabling the development of high-level software. The main goal was to provide easy-to-use tools and hardware interfacing elements, and to put most of the sophistication in the chips and chip sets.","PeriodicalId":191273,"journal":{"name":"Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125856518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An evolvable hardware chip for prosthetic hand controller 一种可进化的假手控制器硬件芯片
I. Kajitani, M. Murakawa, D. Nishikawa, H. Yokoi, N. Kajihara, M. Iwata, D. Keymeulen, H. Sakanashi, T. Higuchi
{"title":"An evolvable hardware chip for prosthetic hand controller","authors":"I. Kajitani, M. Murakawa, D. Nishikawa, H. Yokoi, N. Kajihara, M. Iwata, D. Keymeulen, H. Sakanashi, T. Higuchi","doi":"10.1109/MN.1999.758862","DOIUrl":"https://doi.org/10.1109/MN.1999.758862","url":null,"abstract":"This paper describes an Evolvable Hardware (EHW) chip, and the application of this chip as a controller for a myoelectric prosthetic hand. The chip consists of Genetic Algorithm (GA) hardware, reconfigurable hardware logic, a chromosome memory, a training data memory, and a 16-bit CPU core (NEC V30). This paper also briefly introduces other EHW chips being developed as part of the Ministry of International Trade and Industry's (MITI) Real World Computing Project (RWCP), which include an analogue EHW chip for cellular phones, a neural network EHW chip capable of autonomous reconfiguration, and a data compression EHW chip for electrophotographic printers.","PeriodicalId":191273,"journal":{"name":"Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems","volume":"02 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127272795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
VLSI implementation of an application-specific vision chip for overtake monitoring, real time eye tracking, and automated visual inspection VLSI实现了用于超车监控、实时眼动追踪和自动视觉检查的专用视觉芯片
J. Skribanowitz, T. Knobloch, J. Schreiter, A. Konig
{"title":"VLSI implementation of an application-specific vision chip for overtake monitoring, real time eye tracking, and automated visual inspection","authors":"J. Skribanowitz, T. Knobloch, J. Schreiter, A. Konig","doi":"10.1109/MN.1999.758845","DOIUrl":"https://doi.org/10.1109/MN.1999.758845","url":null,"abstract":"With regard to application-specific constraints such as size, power consumption, and price, many real time vision tasks are still too demanding for today's state-of-the-art hardware. This is especially true for purely digital hardware systems. As an interesting alternative, we investigated the implementation of smart vision algorithms by an application-specific vision chip featuring combined analog and digital processing. The analog part implements computationally intensive operations in a massively parallel array, which allows to realize the remaining operations by a reduced complexity dedicated digital processor. This paper reports on the systematic design and VLSI implementation of dedicated vision chips for automotive image processing, eye tracking, and visual inspection.","PeriodicalId":191273,"journal":{"name":"Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129146983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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