Systolic implementation of a pipelined on-line backpropagation

Abstract

The paper describes the implementation of a systolic array for a multilayer perceptron with a hardware-friendly learning algorithm. A pipelined adaptation of the on-line backpropagation algorithm is shown. It better exploits the parallelism because both the forward and backward phases can be performed simultaneously. As a result, a combined systolic array structure is proposed for both phases. Analytic expressions show that the pipelined version is more efficient than the non-pipelined version. The design is simulated using VHDL at different levels of abstraction to solve three databases and the experimental results agree with analytical estimates. Furthermore, the speed of convergence, the generalization capability and the precision required for both versions are evaluated in order to discuss the neural network performance for the proposed variation-compared with the standard so-called online backpropagation algorithm.