Design and evaluation of a reconfigurable digital architecture for self-organizing maps

Abstract

A digital SIMD architecture to implement Self-Organizing Maps is presented. Custom bit-serial processing elements have been designed not only to obtain a high integration density (an area of 0.06 mm/sup 2/ per PE is estimated for a 0.25 /spl mu/m process and a standard cell design) but also to improve flexibility. The dimensionality of the map, the topological neighbourhood and the kernel function shape are programmable. A modular approach allows several neurochips to be interconnected to expand both the number of neurons and the number of synapses per neuron, performing a mixed synapse/neuron parallelism. In a system composed of a fixed number of neurochips, the number of neurons and synapses physically implemented can be reconfigured in order to achieve the optimal exploitation of hardware resources. The performance of the proposed architecture for fully implemented networks and virtual nets has been evaluated. A significant speedup improvement is achieved in comparison with a similar architecture without synapse parallelism.