Design and evaluation of a reconfigurable digital architecture for self-organizing maps

B. Pino, F. Pelayo, J. Ortega, A. Prieto
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引用次数: 6

Abstract

A digital SIMD architecture to implement Self-Organizing Maps is presented. Custom bit-serial processing elements have been designed not only to obtain a high integration density (an area of 0.06 mm/sup 2/ per PE is estimated for a 0.25 /spl mu/m process and a standard cell design) but also to improve flexibility. The dimensionality of the map, the topological neighbourhood and the kernel function shape are programmable. A modular approach allows several neurochips to be interconnected to expand both the number of neurons and the number of synapses per neuron, performing a mixed synapse/neuron parallelism. In a system composed of a fixed number of neurochips, the number of neurons and synapses physically implemented can be reconfigured in order to achieve the optimal exploitation of hardware resources. The performance of the proposed architecture for fully implemented networks and virtual nets has been evaluated. A significant speedup improvement is achieved in comparison with a similar architecture without synapse parallelism.
自组织地图的可重构数字架构设计与评价
提出了一种实现自组织地图的数字SIMD体系结构。自定义位串行处理元件的设计不仅可以获得高集成密度(对于0.25 /spl mu/m工艺和标准单元设计,估计每PE的面积为0.06 mm/sup 2/),还可以提高灵活性。映射的维数、拓扑邻域和核函数形状是可编程的。模块化方法允许多个神经芯片相互连接,以扩展神经元的数量和每个神经元的突触数量,执行混合突触/神经元并行。在由固定数量的神经芯片组成的系统中,物理实现的神经元和突触数量可以重新配置,以实现硬件资源的最佳利用。对所提出的架构在完全实现的网络和虚拟网络中的性能进行了评估。与没有突触并行性的类似架构相比,实现了显著的加速改进。
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