Proceedings of the Great Lakes Symposium on VLSI 2022最新文献_第9页

Session details: Session 6B: Special Session - 2: Application-oriented Hardware Security Challenges and Solutions 会议详情:6B:专题会议- 2:面向应用的硬件安全挑战与解决方案

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3542693

H. Salmani

引用次数: 0

Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC Platforms 基于图神经网络的SoC平台中间代表硬件木马检测

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530827

Weimin Fu, H. Yu, Orlando Arias, Kaichen Yang, Yier Jin, Tuba Yavuz, Xiaolong Guo

{"title":"Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC Platforms","authors":"Weimin Fu, H. Yu, Orlando Arias, Kaichen Yang, Yier Jin, Tuba Yavuz, Xiaolong Guo","doi":"10.1145/3526241.3530827","DOIUrl":"https://doi.org/10.1145/3526241.3530827","url":null,"abstract":"The rapid growth of the Internet of Things (IoT) industry has increased the demand for intellectual property (IP) cores. Increasing numbers of third-party vendors have raised security concerns for System-on-Chip (SoC) designers. With the growing complexity of SoC design, the workload is overwhelming for SoC designers to diagnose security vulnerabilities manually. Almost all existing SoC platforms are developed using SystemVerilog. However, there is a lack of reliable security static analysis tools for directly processing the SystemVerilog program. Due to its open-source, flexibility and extendability, RISC-V CPU has become an ideal platform for the IoT applications such as wearable devices, entertainment, smart thermostats, etc. As a result, assuring the trustworthiness of a given RISC-V system is highly desired. This paper proposes a graph neural network-based Trojan detection framework to protect the RISC-V SoC platform written in SystemVerilog from intruding malicious logic. The study is under-construction and planned to be validated on the Ariane RISC-V CPU with several peripheral IPs in the experimental section.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123589059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Optimal Region-based Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints 考虑复杂最小植入面积约束的基于区域的混合细胞高度精细布局

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530389

Jie Ma, Wenxin Yu, Zhaoqi Fu, Xin Cheng

引用次数: 0

IMG-SMP: Algorithm and Hardware Co-Design for Real-time Energy-efficient Neural Motion Planning IMG-SMP:实时节能神经运动规划的算法和硬件协同设计

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530367

Lingyi Huang, Xiao Zang, Yu Gong, Chunhua Deng, J. Yi, Bo Yuan

{"title":"IMG-SMP: Algorithm and Hardware Co-Design for Real-time Energy-efficient Neural Motion Planning","authors":"Lingyi Huang, Xiao Zang, Yu Gong, Chunhua Deng, J. Yi, Bo Yuan","doi":"10.1145/3526241.3530367","DOIUrl":"https://doi.org/10.1145/3526241.3530367","url":null,"abstract":"Motion planning is a fundamental and critical task in modern autonomous systems. Conventionally, motion planning is built on uniform sampling that causes long planning procedure. Recently, built upon the powerful learning and representation abilities of deep neural network (DNN), neural motion planners have attracted a lot of attention because of the better biased sampling strategy learned from data. However, the existing NN-based motion planners are facing several limitations, especially the insufficient exploit of critical spatial information and the high computational cost incurred by neural network models. To overcome these limitations, in this paper we propose IMG-SMP, an algorithm and hardware co-design framework for neural sampling-based motion planner. At the algorithm level, IMG-SMP is an end-to-end neural network that can efficiently capture and process the critical spatial correlation to ensure high planning performance. At the hardware level, by properly rescheduling the computing scheme, the dataflow of IMG-SMP architecture can eliminate the unnecessary computations without affecting planning quality. The IMG-SMP hardware accelerator is implemented and synthesized using CMOS 28nm technology. Evaluation results across different planning tasks show that our proposed hardware design achieves order-of-magnitude improvement over CPU and GPU solutions with respect to planning speed, area efficiency and energy efficiency.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125886833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Session details: Session 5B: VLSI Design + VLSI Circuits and Power Aware Design 2 会议详情:会议5B: VLSI设计+ VLSI电路和功耗感知设计2

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3542691

Swaroop Ghosh

引用次数: 0

Hands-On Teaching of Hardware Security for Machine Learning 机器学习硬件安全实践教学

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530828

Ashley Calhoun, E. Ortega, Ferhat Yaman, Anuj Dubey, Aydin Aysu

{"title":"Hands-On Teaching of Hardware Security for Machine Learning","authors":"Ashley Calhoun, E. Ortega, Ferhat Yaman, Anuj Dubey, Aydin Aysu","doi":"10.1145/3526241.3530828","DOIUrl":"https://doi.org/10.1145/3526241.3530828","url":null,"abstract":"Hardware security for machine learning (ML) and artificial intelligence (AI) circuits is becoming a major topic within the cybersecurity framework. Although much research is ongoing on this front, the community omits the educational components. In this paper, we present a training module comprised of a set of hands-on experiments that allow teaching hardware security concepts to newcomers. Specifically, we propose 5 experiments and related training material that teach side-channel attacks and defenses on the hardware implementations of neural networks. We report the organization and the findings after testing these experiments with sophomore undergraduate students at North Carolina State University. The students first study the basics of neural networks and then build a neural network inference circuit on a breadboard. They then conduct a differential power analysis attack on the hardware to steal trained weights and a circuit-balancing (hiding) style defense to mitigate the attack. The students develop all related hardware and software codes to perform attacks and build defenses. The results show that such complex notions of digital circuits design, neural networks, and side-channel analysis can be instructed at the sophomore level with a well-thought set of experiments. Future extensions could include establishing an online infrastructure for remote teaching and efficient scaling to a broader audience.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130703926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Hardware Security in Advanced Manufacturing 先进制造中的硬件安全

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530829

M. Monjur, Joshua Calzadillas, M. Kajol, Qiaoyan Yu

引用次数: 3

HELPSE: Homomorphic Encryption-based Lightweight Password Strength Estimation in a Virtual Keyboard System 虚拟键盘系统中基于同态加密的轻量级密码强度估计

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530338

Michael Cho, Keewoo Lee, Sunwoong Kim

{"title":"HELPSE: Homomorphic Encryption-based Lightweight Password Strength Estimation in a Virtual Keyboard System","authors":"Michael Cho, Keewoo Lee, Sunwoong Kim","doi":"10.1145/3526241.3530338","DOIUrl":"https://doi.org/10.1145/3526241.3530338","url":null,"abstract":"Recently, cyber-physical systems are actively using cloud servers to overcome the limitations of power and processing speed of edge devices. When passwords generated on a client device are evaluated on a server, the information is exposed not only on networks but also on the server-side. To solve this problem, we move the previous lightweight password strength estimation (LPSE) algorithm to a homomorphic encryption (HE) domain. Our proposed method adopts numerical methods to perform the operations of the LPSE algorithm, which is not provided in HE schemes. In addition, the LPSE algorithm is modified to increase the number of iterations of the numerical methods given depth constraints. Our proposed HE-based LPSE (HELPSE) method is implemented as a client-server model. As a client-side, a virtual keyboard system is implemented on an embedded development board with a camera sensor. A password is obtained from this system, encrypted, and sent over a network to a resource-rich server-side. The proposed HELPSE method is performed on the server. Using depths of about 20, our proposed method shows average error rates of less than 1% compared to the original LPSE algorithm. For a polynomial degree of 32K, the execution time on the server-side is about 5 seconds.","PeriodicalId":188228,"journal":{"name":"Proceedings of the Great Lakes Symposium on VLSI 2022","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134404675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference KunlunTVM:一种支持训练和推理的昆仑芯片编译框架

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530316

Jun Zeng, Mingyan Kou, Hailong Yao

引用次数: 0

HetGraph: A High Performance CPU-CGRA Architecture for Matrix-based Graph Analytics HetGraph:基于矩阵的图形分析的高性能CPU-CGRA架构

Proceedings of the Great Lakes Symposium on VLSI 2022 Pub Date : 2022-06-06 DOI: 10.1145/3526241.3530382

Long Tan, Mingyu Yan, Xiaochun Ye, Dongrui Fan

引用次数: 0