2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献_第2页

SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping SafeDE:一个灵活的多样性执行硬件模块轻锁步

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486715

F. Bas, S. Alcaide, Ruben Lorenzo, Guillem Cabo, Guillermo Gil, Oriol Sala, Fabio Mazzocchetti, David Trilla, J. Abella

{"title":"SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping","authors":"F. Bas, S. Alcaide, Ruben Lorenzo, Guillem Cabo, Guillermo Gil, Oriol Sala, Fabio Mazzocchetti, David Trilla, J. Abella","doi":"10.1109/IOLTS52814.2021.9486715","DOIUrl":"https://doi.org/10.1109/IOLTS52814.2021.9486715","url":null,"abstract":"Safety-related systems, such as those in automotive, avionics and space, impose the existence of appropriate safety measures to meet the safety requirements of the system. In the case of the highest integrity level functionalities (e.g. ASIL-D in automotive), diverse redundancy must be deployed to avoid unreasonable risk of a single fault leading the system to a failure (e.g. using lockstepped cores). However, existing lockstep solutions are either (1) highly intrusive and inflexible coupling two cores with hardware means, or (2) costly in terms of execution time and monitoring if a software monitor thread checks that cores running redundantly preserve sufficient staggering. This paper presents SafeDE, a Diversity Enforcement hardware module providing light-lockstep support by means of a non-intrusive and flexible hardware module that preserves staggering across cores running redundant threads, thus bringing time diversity. SafeDE reconciles the lightness and flexibility of software-only solutions, even allowing using the cores without any lockstepping, as well as the tighter staggering of hardware-only solutions that allow using staggering values of few cycles, instead of hundreds of microseconds, as for software-only solutions. Our integration of SafeDE in a RISC-V FPGA-based space multicore from Cobham Gaisler shows that staggering is effectively preserved, and SafeDE overheads are negligible in terms of area and performance due to staggering.","PeriodicalId":185642,"journal":{"name":"2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123290866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

IOLTS 2021 Organizing Committee IOLTS 2021组委会

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/iolts52814.2021.9486683

引用次数: 0

Integrating an Interconnect BIST with Crosstalk Avoidance Hardware 集成互连BIST与串扰避免硬件

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486702

Mahsa Akhsham, Z. Navabi

引用次数: 0

Robust Adaptive Read Scheme for 7nm Configuration SRAMs 7nm配置sram的鲁棒自适应读取方案

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486712

S. Saraswatula, Santosh Yachareni, Shidong Zhou, Narendra Pulipati, Joy Chen, Teja Masina

引用次数: 0

SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation SafeTI:用于MPSoC功能和定时验证的硬件流量注入器

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486689

Oriol Sala, S. Alcaide, Guillem Cabo, F. Bas, Ruben Lorenzo, Pedro Benedicte, David Trilla, Guillermo Gil, Fabio Mazzocchetti, J. Abella

{"title":"SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation","authors":"Oriol Sala, S. Alcaide, Guillem Cabo, F. Bas, Ruben Lorenzo, Pedro Benedicte, David Trilla, Guillermo Gil, Fabio Mazzocchetti, J. Abella","doi":"10.1109/IOLTS52814.2021.9486689","DOIUrl":"https://doi.org/10.1109/IOLTS52814.2021.9486689","url":null,"abstract":"Functional and timing validation of safety-related MPSoCs requires testing specific traffic patterns in the on-chip interconnects. Generally, testing needs to be performed by using software tests whose degree of control on the traffic generated is indirect, and limited to behavior that can be triggered by software, thus often unable to produce traffic generated by peripherals. Therefore, untested traffic scenarios can be abundant and, to a large extent, it is hard to know what traffic scenarios have been effectively tested. This paper presents the safe traffic injector, SafeTI, which allows injecting programmable traffic in AMBA AHB interconnects with high flexibility and degree of control, thus easing achieving high coverage in terms of traffic scenarios tested, and mitigating the uncertainty due to the difficulties to relate software tests with actual traffic scenarios tested. We also integrate successfully the SafeTI in an industrial MPSoC for the space domain proving the effectiveness of the proposed traffic injector.","PeriodicalId":185642,"journal":{"name":"2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129782833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations 一种过程变化感知气体传感和逻辑运算的记忆结构

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486691

S. Khandelwal, M. Ottavi, E. Martinelli, A. Jabir

引用次数: 0

System-Level Test: State of the Art and Challenges 系统级测试:技术现状与挑战

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486708

D. Appello, H. H. Chen, M. Sauer, I. Polian, P. Bernardi, M. Reorda

引用次数: 13

EnSuRe: Energy & Accuracy Aware Fault-tolerant Scheduling on Real-time Heterogeneous Systems 确保:实时异构系统上的能量和精度感知容错调度

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486707

S. Saha, Adewale Adetomi, X. Zhai, Server Kasap, Shoaib Ehsan, T. Arslan, K. Mcdonald-Maier

引用次数: 0

Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing 基于覆盖灰盒模糊的近似计算电路动态验证

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486690

Kazuki Yoshisue, Yutaka Masuda, T. Ishihara

{"title":"Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing","authors":"Kazuki Yoshisue, Yutaka Masuda, T. Ishihara","doi":"10.1109/IOLTS52814.2021.9486690","DOIUrl":"https://doi.org/10.1109/IOLTS52814.2021.9486690","url":null,"abstract":"Approximate computing (AC) has recently emerged as a promising approach to the energy-efficient design of digital systems. For realizing the practical AC design, we need to verify whether the designed circuit can operate correctly under various operating conditions. Namely, the verification needs to efficiently find fatal logic errors or timing errors that violate the constraint of computational quality. This paper proposes a novel dynamic verification methodology of the AC circuit. The key idea of the proposed methodology is to incorporate a quality assessment capability into the Coverage-based Grey-box Fuzzing (CGF). CGF is one of the most promising techniques in the research field of software security testing. By repeating (1) mutation of test patterns, (2) execution of the program under test (PUT), and (3) aggregation of coverage information and feedback to the next test pattern generation, CGF can explore the verification space quickly and automatically. On the other hand, CGF originally cannot consider the computational quality by itself. For overcoming this quality unawareness in CGF, the proposed methodology additionally embeds the Design Under Test (DUT) mechanisms into the calculation part of computational quality. Thanks to the integration of CGF and DUT mechanism, the proposed framework realizes the quality-aware feedback loop in CGF and thus quickly enhances the verification coverage for test patterns that violate the quality constraint. In this work, we quantitatively compared the verification coverage of the approximate arithmetic circuits between the proposed methodology and the random test. In a case study of an approximate multiply-accumulate (MAC) unit, we experimentally confirmed that the proposed methodology achieves the target coverage three times faster than the random test.","PeriodicalId":185642,"journal":{"name":"2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127925657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Addressing Soft Error and Security Threats in DNNs Using Learning Driven Algorithmic Checks 使用学习驱动算法检查解决dnn中的软错误和安全威胁

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486685

C. Amarnath, Md Imran Momtaz, A. Chatterjee

引用次数: 2