2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献_第3页

MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN Accelerators 用零掩蔽输出用于DNN加速器的结构鲁棒性和测试

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486694

Stéphane Burel, A. Evans, L. Anghel

引用次数: 5

Online Fast Detection and Diagnosis of Power Grid Security Attacks Using State Checksums 基于状态校验和的电网安全攻击在线快速检测与诊断

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486696

Suvadeep Banerjee, A. Chatterjee

{"title":"Online Fast Detection and Diagnosis of Power Grid Security Attacks Using State Checksums","authors":"Suvadeep Banerjee, A. Chatterjee","doi":"10.1109/IOLTS52814.2021.9486696","DOIUrl":"https://doi.org/10.1109/IOLTS52814.2021.9486696","url":null,"abstract":"State information transmitted across communication links of distributed power grids can be compromised by security attacks on these links causing power fluctuations and outage. Encryption of transmitted data is a first line of defense against such attacks but the entire network can be compromised if the keys are broken such as through side-channel attacks on encryption hardware. We propose the use of low cost state checksums as a critical second line of defense against such attacks. It is seen that stealth and replay attacks that can defeat prior residual filter based attack detection methods, can be detected using state checksums. Further, the proposed attack detection approach is highly resilient to adversarial counterattacks. A key benefit is low latency diagnosis of compromised communication links (and thereby sub-networks) not possible through use of encryption techniques alone. Diagnosis is driven by a dynamic binary search driven partitioning of system states into compromised vs. nominal subsets. We demonstrate through simulation of IEEE benchmark systems and two high-voltage power grids that our proposed scheme significantly reduces the latency of attack mitigation with lower complexity in comparison to prior research.","PeriodicalId":185642,"journal":{"name":"2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127677918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method 金属比等效时间采样:一种高效的波形采集方法

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486692

Shuhei Yamamoto, Yuto Sasaki, Yujie Zhao, Jianglin Wei, A. Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Takayuki Nakatani, MinhTri Tran, Shogo Katayama, K. Hatayama, Haruo Kobayashi

引用次数: 2

Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems 基于模型的数字系统安全评估的功能失调模型自动提取

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486705

Tiziano Fiorucci, J. Daveau, G. D. Natale, P. Roche

引用次数: 3

Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing 利用近似计算减少三模冗余的过剩供给

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486699

B. Deveautour, Marcello Traiola, A. Virazel, P. Girard

{"title":"Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing","authors":"B. Deveautour, Marcello Traiola, A. Virazel, P. Girard","doi":"10.1109/IOLTS52814.2021.9486699","DOIUrl":"https://doi.org/10.1109/IOLTS52814.2021.9486699","url":null,"abstract":"Until recently, Approximate Computing (AxC) was considered to be a trend topic mainly for resilient applications. Its use aimed at reducing area and power consumption of Integrated Circuits (ICs) at the cost of a reduced accuracy. Beside, AxC-based fault-tolerance has also emerged recently to save area et power consumption w.r.t. conventional fault-tolerance at the cost of a reduced reliability level. Therefore, approximate fault-tolerance is restricted to non-critical applications. In a previous work, a Quadruple Approximate Modular Redundancy (QAMR) scheme, based on using four approximate circuit copies, was proposed. In a single fault scenario, it provides the same reliability level as Triple Modular Redundancy (TMR). Moreover, QAMR allows reducing area and power consumption costs w.r.t. TMR in many cases. In this paper, we study the occurrence of multiple faults, and compare the QAMR and TMR behaviors. Experimental results highlight the TMR overprovision (i.e. it provides more redundancy than necessary) and show how the QAMR approach can reduce it. Moreover, a thorough analysis of the results shows that a high tolerance to multiple faults is associated to a large circuit area and to a lower percentage of logic shared among different fan-in cones of the circuit outputs.","PeriodicalId":185642,"journal":{"name":"2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"282 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132972784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A New Domains-based Isolation Design Flow for Reconfigurable SoCs 一种基于域的可重构soc隔离设计流程

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486687

A. Portaluri, C. D. Sio, S. Azimi, L. Sterpone

{"title":"A New Domains-based Isolation Design Flow for Reconfigurable SoCs","authors":"A. Portaluri, C. D. Sio, S. Azimi, L. Sterpone","doi":"10.1109/IOLTS52814.2021.9486687","DOIUrl":"https://doi.org/10.1109/IOLTS52814.2021.9486687","url":null,"abstract":"Reconfigurable SoCs are widely adopted in mission-critical tasks in aerospace and automotive. Though, one of their main drawbacks is the susceptibility to high-energy particles both in space and at sea level. Isolation Design Flow is a promising implementation approach to improve the reliability of circuits. However, considering the high number of modules in a complex circuit, especially when redundant techniques are applied, IDF requires a complex floorplanning stage. In this paper, the benefits of using IDF are evaluated, both for plain and hardened-by-redundancy designs. We propose an implementation methodology to tackle the complexity of applying IDF to TMR-based circuits that usually make the implementation approach unfeasible. The impact of different design policies on the reliability of the system is evaluated through fault injection campaigns. The proposed method is applied to the TMR-hardened CORDIC core implemented on Zynq AP-SoC and compared with other possible solutions. The results report a significant improvement in the TMR effectiveness when the proposed domains-based IDF is applied.","PeriodicalId":185642,"journal":{"name":"2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131201282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Protecting GPU's Microarchitectural Vulnerabilities via Effective Selective Hardening 通过有效的选择性加固保护GPU的微架构漏洞

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486703

J. E. R. Condia, P. Rech, F. Santos, L. Carro, M. Reorda

{"title":"Protecting GPU's Microarchitectural Vulnerabilities via Effective Selective Hardening","authors":"J. E. R. Condia, P. Rech, F. Santos, L. Carro, M. Reorda","doi":"10.1109/IOLTS52814.2021.9486703","DOIUrl":"https://doi.org/10.1109/IOLTS52814.2021.9486703","url":null,"abstract":"Graphics Processing Units (GPUs) are today adopted in several domains for which reliability is fundamental, such as self-driving cars and autonomous machines. Unfortunately, on one side GPUs have been shown to have a high error rate and, on the other side, the constraints imposed by real-time safety-critical applications make traditional, costly, replication-based hardening solutions inadequate. This paper proposes an effective microarchitectural selective hardening of GPU modules to mitigate those faults that affect instructions correct execution. We first characterize, through Register-Transfer Level (RTL) fault injections, the architectural vulnerabilities of a GPU model (FlexGripPlus). We specifically target transient faults in the functional units and pipeline registers of a GPU core. Then, we apply selective hardening by triplicating the locations in each module that we found to be more critical. The results show that selective hardening using Triple Modular Redundancy (TMR) can correct 85% to 99% of faults in the pipeline registers and from 50% to 100% of faults in the functional units. The proposed selective TMR strategy reduces the hardware overhead by up to 65% when compared with traditional TMR.","PeriodicalId":185642,"journal":{"name":"2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116469573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement 提高流水线处理器过渡故障覆盖率的自检库分析

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486711

R. Cantoro, P. Girard, Riccardo Masante, Sandro Sartoni, M. Reorda, A. Virazel

引用次数: 4

IOLTS 2021 Foreword

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/iolts52814.2021.9486709

引用次数: 0

Unsupervised Recycled FPGA Detection Based on Direct Density Ratio Estimation 基于直接密度比估计的无监督回收FPGA检测

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486698

Y. Isaka, Foisal Ahmed, Michihiro Shintani, M. Inoue

{"title":"Unsupervised Recycled FPGA Detection Based on Direct Density Ratio Estimation","authors":"Y. Isaka, Foisal Ahmed, Michihiro Shintani, M. Inoue","doi":"10.1109/IOLTS52814.2021.9486698","DOIUrl":"https://doi.org/10.1109/IOLTS52814.2021.9486698","url":null,"abstract":"With the expansion of the semiconductor supply chain, recycled field-programmable gate arrays (FPGAs) have become a serious concern. Several methods for detecting recycled FPGAs by analyzing the ring oscillator (RO) frequencies have been proposed; however, most assume the presence of known fresh FPGAs (KFFs) as the training data used for machine-learning-based classification, which is an impractical assumption. In this study, we propose a novel KFF-free recycled FPGA detection method based on an unsupervised anomaly detection scheme. As the RO frequencies in the neighboring logic blocks on an FPGA are similar because of systematic process variation, our method compares the RO frequencies and does not require KFFs. The proposed method efficiently identifies recycled FPGAs through outlier detection using direct density ratio estimation. Experiments using Xilinx Artix-7 FPGAs demonstrate that the proposed method successfully distinguishes two recycled FPGAs from 10 fresh FPGAs. In contrast, a conventional KFF-free recycled FPGA detection method results in certain misclassification.","PeriodicalId":185642,"journal":{"name":"2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133765832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4