2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)最新文献_第4页

Hardware-Trojan Classification based on the Structure of Trigger Circuits Utilizing Random Forests 基于随机森林触发电路结构的硬件木马分类

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486700

Tatsuki Kurihara, N. Togawa

{"title":"Hardware-Trojan Classification based on the Structure of Trigger Circuits Utilizing Random Forests","authors":"Tatsuki Kurihara, N. Togawa","doi":"10.1109/IOLTS52814.2021.9486700","DOIUrl":"https://doi.org/10.1109/IOLTS52814.2021.9486700","url":null,"abstract":"Recently, with the spread of Internet of Things (IoT) devices, embedded hardware devices have been used in a variety of everyday electrical items. Due to the increased demand for embedded hardware devices, some of the IC design and manufacturing steps have been outsourced to third-party vendors. Since malicious third-party vendors may insert malicious circuits, called hardware Trojans, into their products, developing an effective hardware Trojan detection method is strongly required. In this paper, we propose 25 hardware-Trojan features based on the structure of trigger circuits for machine-learning-based hardware Trojan detection. Combining the proposed features into 11 existing hardware-Trojan features, we totally utilize 36 hardware-Trojan features for classification. Then we classify the nets in an unknown netlist into a set of normal nets and Trojan nets based on the random-forest classifier. The experimental results demonstrate that the average true positive rate (TPR) becomes 63.6% and the average true negative rate (TNR) becomes 100.0%. They improve the average TPR by 14.7 points while keeping the average TNR compared to existing state-of-the-art methods. In particular, the proposed method successfully finds out Trojan nets in several benchmark circuits, which are not found by the existing method.","PeriodicalId":185642,"journal":{"name":"2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"404 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124311658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level Netlists 基于机器学习的门级网络中硬件木马检测的数据增强

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486713

Kento Hasegawa, Seira Hidano, Kohei Nozawa, S. Kiyomoto, N. Togawa

引用次数: 1

CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models 基于CDF距离的非线性延迟变化模型统计参数提取

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486684

Kensuke Murakami, Mahfuzul Islam, H. Onodera

引用次数: 1

FPGA Checkpointing for Scientific Computing 科学计算的FPGA检查点

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486693

Marc Perelló Bacardit, L. Bautista-Gomez, O. Unsal

{"title":"FPGA Checkpointing for Scientific Computing","authors":"Marc Perelló Bacardit, L. Bautista-Gomez, O. Unsal","doi":"10.1109/IOLTS52814.2021.9486693","DOIUrl":"https://doi.org/10.1109/IOLTS52814.2021.9486693","url":null,"abstract":"The use of FPGAs in computational workloads is becoming increasingly popular due to the flexibility of these devices in comparison to ASICs, and their low power consumption compared to GPUs and CPUs. However, scientific applications run for long periods of time and the hardware is always subject to failures due to either soft or hard errors. Thus, it is important to protect these long running jobs with fault tolerance mechanisms. Checkpoint-Restart is a popular technique in high-performance computing that allows large scale applications to cope with frequent failures. In this work we approach the fault tolerance of CPU-FPGA heterogeneous applications from a high level by using OmpSs@FPGA environment and a multi-level checkpointing library. We analyse the performance of several different applications and we understand what kind of overheads we can expect from checkpointing computational workloads running on FPGAs. Our results demonstrate overheads as low as 0.16% and 0.66% when checkpointing very frequently, indicating that this technique is efficient and does not add a significant amount of overhead to the system. In addition, we showcase a proof of concept for checkpointing partial data of the FPGA task itself. This can prove useful for workloads in which most data is offloaded to the FPGA memory at once and do not constantly move all the data between the accelerator and the CPU.","PeriodicalId":185642,"journal":{"name":"2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117161814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Towards Error Resilient and Power-Efficient Adaptive Multiprocessor System using Highly Configurable and Flexible Cross-Layer Framework 采用高度可配置和灵活的跨层框架实现容错和节能的自适应多处理器系统

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486695

M. Veleski, M. Hübner, M. Krstic, R. Kraemer

{"title":"Towards Error Resilient and Power-Efficient Adaptive Multiprocessor System using Highly Configurable and Flexible Cross-Layer Framework","authors":"M. Veleski, M. Hübner, M. Krstic, R. Kraemer","doi":"10.1109/IOLTS52814.2021.9486695","DOIUrl":"https://doi.org/10.1109/IOLTS52814.2021.9486695","url":null,"abstract":"A typical multiprocessor system often needs to support a wide spectrum of applications. Today, error resilience and low power consumption are two crucial, but non-complementary requirements and meeting both simultaneously is difficult. Thus, adaptivity is becoming increasingly important feature for modern computing systems. In this regard, we integrate a highly-configurable framework with a set of cross-layer techniques efficient in improving error resilience / power consumption into a multiprocessor system. The framework intelligently interchanges methods such as Adaptive Voltage and Frequency Scaling (AVFS), Triple Modular Redundancy (TMR) and clock-gating while the system is on-line. Additionally, flexibility as an inherent multiprocessor feature enables dynamical adaptation of the system to the current requirements. Putting all together, a balanced level between the two key metrics is achieved. We conduct numerous experiments to show the advantages of the proposed approach. Finally, we use the results to confirm the benefits and the effectiveness of the framework.","PeriodicalId":185642,"journal":{"name":"2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132199417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay 考虑线延迟影响的FPGA芯片过程变化测量方法

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-06-28 DOI: 10.1109/IOLTS52814.2021.9486686

Y. Miura, S. Tsutsumi

引用次数: 0

High-level Intellectual Property Obfuscation via Decoy Constants 通过诱饵常量进行高级知识产权混淆

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) Pub Date : 2021-05-13 DOI: 10.1109/IOLTS52814.2021.9486714

L. Aksoy, Quang-Linh Nguyen, Felipe Almeida, J. Raik, M. Flottes, Sophie Dupuis, S. Pagliarini

{"title":"High-level Intellectual Property Obfuscation via Decoy Constants","authors":"L. Aksoy, Quang-Linh Nguyen, Felipe Almeida, J. Raik, M. Flottes, Sophie Dupuis, S. Pagliarini","doi":"10.1109/IOLTS52814.2021.9486714","DOIUrl":"https://doi.org/10.1109/IOLTS52814.2021.9486714","url":null,"abstract":"This paper presents a high-level circuit obfuscation technique to prevent the theft of intellectual property (IP) of integrated circuits. In particular, our technique protects a class of circuits that relies on constant multiplications, such as neural networks and filters, where the constants themselves are the IP to be protected. By making use of decoy constants and a key-based scheme, a reverse engineer adversary at an untrusted foundry is rendered incapable of discerning true constants from decoys. The time-multiplexed constant multiplication (TMCM) block of such circuits, which realizes the multiplication of an input variable by a constant at a time, is considered as our case study for obfuscation. Furthermore, two TMCM design architectures are taken into account; an implementation using a multiplier and a multiplierless shift-adds implementation. Optimization methods are also applied to reduce the hardware complexity of these architectures. The well-known satisfiability (SAT) and automatic test pattern generation (ATPG) based attacks are used to determine the vulnerability of the obfuscated designs. It is observed that the proposed technique incurs small overheads in area, power, and delay that are comparable to the hardware complexity of prominent logic locking methods. Yet, the advantage of our approach is in the insight that constants - instead of arbitrary circuit nodes - become key-protected.","PeriodicalId":185642,"journal":{"name":"2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115582864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4