Robust Adaptive Read Scheme for 7nm Configuration SRAMs

Abstract

This paper presents a new Adaptive Read scheme for Configuration SRAMs with a feedback mechanism to eliminate Read-Disturb, enhancing Read Margin, yield and performance. The proposed scheme is implemented on TSMC 7nm FinFETs for Configuration SRAMs in Xilinx FPGAs, and this idea is applicable to any distributed SRAM structures. The design has an intrinsic dynamic feedback mechanism to adjust the read address voltage effectively, based on the process, voltage and temperature (PVT), by using a special replica memory cell that emulates actual memory cells. The proposed Op-Amp based design with a memory cell emulating circuit in the negative feedback is shown to be working on silicon, which tunes pass-gate (PG) address voltage during read, with 2.7x improvement in read margin, and also avoids read-disturb.