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Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232)最新文献

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Off chip monitors and built in current sensors for analogue and mixed signal testing 片外监视器和内置电流传感器模拟和混合信号测试
Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232) Pub Date : 1998-11-12 DOI: 10.1109/IDDQ.1998.730758
Y. Maidon, Y. Deval, H. Manhaeve
{"title":"Off chip monitors and built in current sensors for analogue and mixed signal testing","authors":"Y. Maidon, Y. Deval, H. Manhaeve","doi":"10.1109/IDDQ.1998.730758","DOIUrl":"https://doi.org/10.1109/IDDQ.1998.730758","url":null,"abstract":"The aim of this paper is to be part a general survey regarding test methods for analogue and mixed circuits, using a stimulus on the signal or power supply inputs. The data is extracted from the power supply current I/sub DD/. It is based on the fruitful measurement of the I/sub DDQ/, the DC power supply current, as well as the measurement of the I/sub DDT/, the transient power supply current. This paper presents the state of the art of the existing current monitors sorted according to their sensitive element.","PeriodicalId":183890,"journal":{"name":"Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131892242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
CMOS SRAM functional test with quiescent write supply current CMOS SRAM静态写电源电流功能测试
Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232) Pub Date : 1998-11-12 DOI: 10.1109/IDDQ.1998.730724
M. Hashizume, T. Tamesada, T. Koyama, A. van de Goor
{"title":"CMOS SRAM functional test with quiescent write supply current","authors":"M. Hashizume, T. Tamesada, T. Koyama, A. van de Goor","doi":"10.1109/IDDQ.1998.730724","DOIUrl":"https://doi.org/10.1109/IDDQ.1998.730724","url":null,"abstract":"A large quiescent supply current of mA order flows when a data is written in a CMOS SRAM IC. In this paper an SRAM test method is proposed which is based on the supply current and whose purpose is to detect logically faulty IC's. The method is evaluated by some experiments. In the experiments, about 80% of faulty CMOS SRAM IC's are detected. Also it is shown that the total test time can be reduced if the method is used in the pretest stage of a functional test.","PeriodicalId":183890,"journal":{"name":"Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133175322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design-for-Iddq-testing for embedded cores based system-on-a-chip 基于片上系统的嵌入式内核iddq测试设计
Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232) Pub Date : 1998-11-12 DOI: 10.1109/IDDQ.1998.730769
R. Rajsuman
{"title":"Design-for-Iddq-testing for embedded cores based system-on-a-chip","authors":"R. Rajsuman","doi":"10.1109/IDDQ.1998.730769","DOIUrl":"https://doi.org/10.1109/IDDQ.1998.730769","url":null,"abstract":"System-on-a-chip (SoC) ICs in deep submicron technologies present major challenges in the implementation of Iddq testing. The problems are increased leakage current due to increasing number of gates as well as due to increased sub-threshold leakage of the individual transistors. While methods such as substrate-bias and low temperature are adequate to reduce sub-threshold leakage in deep submicron technologies, almost no solution is available to address the issue of increased leakage due to enormous size of the SoC design. In this paper, we first present a design-for-test concept to address the issue of high leakage due to the large size of SoC design. Secondly, we provide some design rules that are necessary to make SoC design suitable for Iddq testing. The design methodology presented in this paper facilitates Iddq testing by controlling power-supply of the individual cores through JTAG boundary scan and allows Iddq testing on one core at a time. The design does not require any dedicated pin for this control and area overhead is negligible.","PeriodicalId":183890,"journal":{"name":"Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232)","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127417490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Test input generation for supply current testing of bridging faults in bipolar combinational logic circuits 双极组合逻辑电路中桥接故障的电源电流测试输入产生
Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232) Pub Date : 1998-11-12 DOI: 10.1109/IDDQ.1998.730726
T. Kuchii, M. Hashizume, T. Tamesada
{"title":"Test input generation for supply current testing of bridging faults in bipolar combinational logic circuits","authors":"T. Kuchii, M. Hashizume, T. Tamesada","doi":"10.1109/IDDQ.1998.730726","DOIUrl":"https://doi.org/10.1109/IDDQ.1998.730726","url":null,"abstract":"A test input generation algorithm for supply current tests is proposed to detect bridging faults in bipolar combinational circuits. By using the algorithm, test input vectors are derived for ISCAS-85 benchmark circuits, which are implemented on printed boards. It is shown by the test generation that more faults in bipolar circuits can be detected with a smaller number of test input vectors than a conventional test method based on output logic values.","PeriodicalId":183890,"journal":{"name":"Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121149828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An automated technique to identify defective CMOS devices based on linear regression analysis of transient signal data 基于瞬态信号数据线性回归分析的CMOS缺陷器件自动识别技术
Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232) Pub Date : 1998-11-12 DOI: 10.1109/IDDQ.1998.730729
J. Plusquellic, D. Chiarulli, S. Levitan
{"title":"An automated technique to identify defective CMOS devices based on linear regression analysis of transient signal data","authors":"J. Plusquellic, D. Chiarulli, S. Levitan","doi":"10.1109/IDDQ.1998.730729","DOIUrl":"https://doi.org/10.1109/IDDQ.1998.730729","url":null,"abstract":"Transient signal analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points and on I/sub DD/ switching transients on the supply rails. We show that it is possible to identify defective devices by analyzing the transient signals measured at test points on paths not sensitized from the defect site. The small signal variations generated at these test points are analyzed in both the time and frequency domain. Linear regression analysis is used to show the absence of correlation in these signals across the outputs of bridging and open drain defective devices. A statistical method and an algorithm for identifying defective devices are presented that is based on the standard deviation of regression residuals computed over a compressed representation of these signals.","PeriodicalId":183890,"journal":{"name":"Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232)","volume":"11 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131968385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Static test compaction for IDDQ testing of sequential circuits 顺序电路IDDQ测试用静态测试压实
Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232) Pub Date : 1998-11-12 DOI: 10.1109/IDDQ.1998.730725
Y. Higami, K. Saluja, K. Kinoshita
{"title":"Static test compaction for IDDQ testing of sequential circuits","authors":"Y. Higami, K. Saluja, K. Kinoshita","doi":"10.1109/IDDQ.1998.730725","DOIUrl":"https://doi.org/10.1109/IDDQ.1998.730725","url":null,"abstract":"This paper presents a static test compaction method for IDDQ testing of sequential circuits. Target faults are bridging faults between arbitrary pair of nodes including internal nodes, signal lines, VDD and GND. In the proposed method, test subsequences are removed and replaced with shorter subsequences.","PeriodicalId":183890,"journal":{"name":"Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128036128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI 一种基于电荷存储BICS电路的深亚微米CMOS ULSI IDDQ测试新方案
Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232) Pub Date : 1998-11-12 DOI: 10.1109/IDDQ.1998.730757
Chih-Wen Lu, Chung-Len Lee, J. Chen, C. Su
{"title":"A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI","authors":"Chih-Wen Lu, Chung-Len Lee, J. Chen, C. Su","doi":"10.1109/IDDQ.1998.730757","DOIUrl":"https://doi.org/10.1109/IDDQ.1998.730757","url":null,"abstract":"In this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability.","PeriodicalId":183890,"journal":{"name":"Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115026936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Model-based I/sub DDQ/ pass/fail limit setting 基于模型的I/sub DDQ/通过/失败限制设置
Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232) Pub Date : 1998-11-12 DOI: 10.1109/IDDQ.1998.730731
T. A. Unni, D. Walker
{"title":"Model-based I/sub DDQ/ pass/fail limit setting","authors":"T. A. Unni, D. Walker","doi":"10.1109/IDDQ.1998.730731","DOIUrl":"https://doi.org/10.1109/IDDQ.1998.730731","url":null,"abstract":"This paper describes several methods for setting LDDQ pass/fail limits using cell-based process, circuit and logic simulation. We demonstrate trade-offs in accuracy and model building effort on the ISCAS85 circuits.","PeriodicalId":183890,"journal":{"name":"Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127745859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
100 MHz IDDQ sensor design with 1 /spl mu/A resolution for BIST applications 100 MHz IDDQ传感器设计，分辨率为1 /spl mu/A，适用于BIST应用
Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232) Pub Date : 1998-11-12 DOI: 10.1109/IDDQ.1998.730767
Y. Antonioli, K. Kinoshita, S. Nishikawa, H. Uemura
{"title":"100 MHz IDDQ sensor design with 1 /spl mu/A resolution for BIST applications","authors":"Y. Antonioli, K. Kinoshita, S. Nishikawa, H. Uemura","doi":"10.1109/IDDQ.1998.730767","DOIUrl":"https://doi.org/10.1109/IDDQ.1998.730767","url":null,"abstract":"This paper presents a high-speed high-resolution I/sub DDQ/ (power supply quiescent current) sensor design for BIST (built-in self test) applications. The voltage drop is amplified before comparison with a reference voltage to improve sensing resolution. For various CUTs (Circuits Under Test) including Iscas circuits, Spice simulations show speeds up to 100 MHz. A resolution better than 1 /spl mu/A is achieved while the voltage drop is kept under 0.3 V.","PeriodicalId":183890,"journal":{"name":"Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132232913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Clustering based identification of faulty ICs using I/sub DDQ/ tests 使用I/sub DDQ/测试的基于聚类的故障ic识别
Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232) Pub Date : 1998-11-12 DOI: 10.1109/IDDQ.1998.730756
S. Jandhyala, H. Balachandran, S. Menon, A. Jayasumana
{"title":"Clustering based identification of faulty ICs using I/sub DDQ/ tests","authors":"S. Jandhyala, H. Balachandran, S. Menon, A. Jayasumana","doi":"10.1109/IDDQ.1998.730756","DOIUrl":"https://doi.org/10.1109/IDDQ.1998.730756","url":null,"abstract":"Technological advances in design and process have led to questions being raised about the applicability of I/sub DDQ/ testing. The main concern is the inability to differentiate between normal and faulty quiescent currents in ICs. In this paper, we propose a new methodology aimed at addressing this concern through the application of clustering techniques to identify ICs with abnormal I/sub DDQ/ values. Preliminary results of applying this technique in production test are also presented.","PeriodicalId":183890,"journal":{"name":"Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121687943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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