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2013 Proceedings of the ESSCIRC (ESSCIRC)最新文献

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Switching-based charger with continuously built-in resistor detector (CBIRD) and analog multiplication-division unit (AMDU) for fast charging in Li-Ion battery 具有连续内置电阻检测器(CBIRD)和模拟乘除单元(AMDU)的锂离子电池快速充电开关充电器
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649096
Ruei-Hong Peng, Tsu-Wei Tsai, Ke-Horng Chen, Zhih Han Tai, Yi Hsuan Cheng, Chi Chung Tsai, Hsin-Yu Luo, Shih-Ming Wang, Long-Der Chen, Cheng-Chen Yang, Jui-Lung Chen
{"title":"Switching-based charger with continuously built-in resistor detector (CBIRD) and analog multiplication-division unit (AMDU) for fast charging in Li-Ion battery","authors":"Ruei-Hong Peng, Tsu-Wei Tsai, Ke-Horng Chen, Zhih Han Tai, Yi Hsuan Cheng, Chi Chung Tsai, Hsin-Yu Luo, Shih-Ming Wang, Long-Der Chen, Cheng-Chen Yang, Jui-Lung Chen","doi":"10.1109/ESSCIRC.2013.6649096","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649096","url":null,"abstract":"Proposed continuously built-in resistor detector (CBIRD) monitors the built-in resistance (BIR) of the Li-Ion batteries for achieving fast charging process. Owing to the detection of the battery built-in resistance in real-time, the transition from the constant-current (CC) mode to the constant-voltage (CV) mode can be postponed to have large energy storing in the battery, Thus, the charging time of the switching-based charger can be effectively reduced. The CBIRD is composed of four analog circuits, which are the differentiator, the subtraction sample-and-hole (S/H), analog multiplication-division unit (AMDU), and voltage adder for accurate BIR detection. Thus, the proposed switching-based charger with the CBIRD has 45% charging time improvement for Li-ion batteries.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122783149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
High temperature-low temperature coefficient analog voltage reference integrated circuit implemented with SiC MESFETs 用SiC mesfet实现高温-低温系数模拟电压参考集成电路
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649164
V. Banu, P. Godignon, M. Alexandru, M. Vellvehí, X. Jordà, J. Millán
{"title":"High temperature-low temperature coefficient analog voltage reference integrated circuit implemented with SiC MESFETs","authors":"V. Banu, P. Godignon, M. Alexandru, M. Vellvehí, X. Jordà, J. Millán","doi":"10.1109/ESSCIRC.2013.6649164","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649164","url":null,"abstract":"A high temperature compensated voltage reference integrated circuit (IC), was designed and for the first time fabricated on silicon carbide (SiC) material, using MESFET devices. A planar finger type MESFET was developed for this purpose. The schematic and the principle of the presented circuit is based on a new concept that replace the typical bandgap reference and avoid the necessity of using an operational amplifier (OpAmp), which is not yet developed on SiC. The experimental temperature coefficient (TC) is significantly better than a Zener diode and comparable to the normal bandgap voltage references on silicon, but the present circuit is able to work up to 300°C. The circuit contains also a linearized temperature sensor.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128777439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
On-chip temperature compensation of driver voltage for LC-displays 液晶显示器驱动电压的片上温度补偿
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649083
R. Becker, A. Zhelyazkov, Bernie Kim
{"title":"On-chip temperature compensation of driver voltage for LC-displays","authors":"R. Becker, A. Zhelyazkov, Bernie Kim","doi":"10.1109/ESSCIRC.2013.6649083","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649083","url":null,"abstract":"Liquid-Crystal Displays (LCDs) can exhibit a strong variation of optical performance parameters as a function of temperature. We present driver circuitry, which comprises a temperature sensor and the appropriate signal-processing to compensate for this behaviour.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128213818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.25-mm CMOS, 7-ppm/°C, 8-mA quiescent current, ±5-mA output current low-dropout voltage regulator 0.25 mm CMOS, 7 ppm/°C, 8 ma静态电流，±5 ma输出电流低降稳压器
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649081
F. Conso, G. Rescio, M. Grassi, C. Ribellino, G. Billè, A. Rizzo, S. Petenyi, S. Privitera, P. Malcovati
{"title":"A 0.25-mm CMOS, 7-ppm/°C, 8-mA quiescent current, ±5-mA output current low-dropout voltage regulator","authors":"F. Conso, G. Rescio, M. Grassi, C. Ribellino, G. Billè, A. Rizzo, S. Petenyi, S. Privitera, P. Malcovati","doi":"10.1109/ESSCIRC.2013.6649081","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649081","url":null,"abstract":"This paper presents a low-dropout voltage regulator capable of delivering ±5 mA to the load with a quiescent current as low as 8 μA and a temperature coefficient equal to 7-ppm/°C, over a temperature range from -40 °C to +125 °C. The output voltage can be either 1.25 V or 1.8 V, while the input voltage can range from 1.8 V to 5.5 V. The bipolar output current is achieved by using a class-AB error amplifier with a quiescent current control circuit based on a translinear loop. The low temperature coefficient is guaranteed by a current mode bandgap circuit with curvature compensation.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126851084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
EMI resisting voltage regulator with large signal PSR up to 1GHz 抗EMI稳压器，大信号PSR高达1GHz
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649155
F. Michel, M. Steyaert
{"title":"EMI resisting voltage regulator with large signal PSR up to 1GHz","authors":"F. Michel, M. Steyaert","doi":"10.1109/ESSCIRC.2013.6649155","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649155","url":null,"abstract":"A voltage regulator is introduced that exhibits large signal (25 dBm) power supply rejection (PSR) up to 1GHz to comply with current electromagnetic compatibility (EMC) standards [1]. Negative peak cut-off using a rectifying diode is demonstrated so that line disturbances of several volts can be tolerated while still maintaining positive drop-out voltage. In order to avoid electromagnetic interference (EMI) at the output the regulator is realized in an output capacitor-less topology, thus decoupled only internally by a 200 pF on-chip capacitor. The regulator was implemented in 0.18 μm HV CMOS and draws a quiescent current of 240 μA at 4V supply while delivering up to 5mA load current at a nominal output of 3.3V.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"80 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134273570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An autonomous piezoelectric energy harvesting IC based on a synchronous multi-shots technique 基于同步多镜头技术的自主压电能量采集集成电路
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649157
P. Gasnier, J. Willemin, S. Boisseau, G. Despesse, C. Condemine, Guillaume Gouvernet, J. Chaillout
{"title":"An autonomous piezoelectric energy harvesting IC based on a synchronous multi-shots technique","authors":"P. Gasnier, J. Willemin, S. Boisseau, G. Despesse, C. Condemine, Guillaume Gouvernet, J. Chaillout","doi":"10.1109/ESSCIRC.2013.6649157","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649157","url":null,"abstract":"This paper presents a fully autonomous integrated circuit (IC) dedicated to piezoelectric harvesters. The IC implements a novel Synchronous Electric Charge Extraction (SECE) technique which optimizes the energy transfer from a highly charged piezoelectric harvester to a low voltage storage element. The system deals with piezoelectric powers in the range of 10 μW to 1mW and handles very high piezoelectric voltage values (>100V) limited by the off-chip components around the IC. The IC has been fabricated in AMS 0.35 μ m3.3V technology and its low power consumption (1 μW @ 5Hz) is particularly suitable for low frequency harvesters. The Multi-Shots SECE (MS-SECE) technique implemented in the IC increases the efficiency by up to 25% compared to a standard SECE technique and allows the use of small off-chip components. An efficiency of 61% has been reached with a 125mm3coupled inductor @ 40V. Moreover, the complete system self-starts and works without any battery.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132977967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 0.039mm2 inverter-based 1.82mW 68.6dB-SNDR 10MHz-BW CT-ΣΔ-ADC in 65nm CMOS 基于0.039mm2逆变器的1.82mW 68.6dB-SNDR 10MHz-BW CT-ΣΔ-ADC, 65nm CMOS
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649137
Sebastian Zeller, Christian Muenker, R. Weigel
{"title":"A 0.039mm2 inverter-based 1.82mW 68.6dB-SNDR 10MHz-BW CT-ΣΔ-ADC in 65nm CMOS","authors":"Sebastian Zeller, Christian Muenker, R. Weigel","doi":"10.1109/ESSCIRC.2013.6649137","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649137","url":null,"abstract":"We propose design techniques for the realization of power- and area-efficient CT-ΣΔ-ADCs in ultra deep submicron CMOS: A resonant single-opamp 3rd order integrator with loss compensation, an inverter-based opamp with digitally-assisted biasing and common mode control, a pseudo-differential modulator topology with quasi-1.5-bit quantization and FIR-DACs with passive DT compensation. A highly compact 41.4 fJ/conv.-step, 77 dB-SFDR, 1.1 V ADC has been implemented to prove these concepts. The entire active analog circuitry in this minimalistic 3rd order modulator consists of only 10 CMOS inverters.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123208490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A low power zero-crossing pipeline-SAR ADC with on-chip dynamically loaded pre-charged reference 具有片上动态加载预充电基准的低功耗过零管道sar ADC
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649085
J. Kuppambatti, P. Kinget
{"title":"A low power zero-crossing pipeline-SAR ADC with on-chip dynamically loaded pre-charged reference","authors":"J. Kuppambatti, P. Kinget","doi":"10.1109/ESSCIRC.2013.6649085","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649085","url":null,"abstract":"A dynamically loaded pre-charged reference technique for low power zero-crossing pipeline-SAR ADCs is presented. Power hungry reference buffers are eliminated and the loading from the reference capacitors is also reduced, thus improving the ADC noise performance. The 65-nm CMOS ADC prototype has an SFDR/SNR/SNDR of 77dB/70dB/66dB at 25MHz, while consuming 4.8mW at 50MS/s, including all the power for the reference generation and distribution.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123825694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A high-throughput 16× super resolution processor for real-time object recognition SoC 高通量16×超分辨率处理器，用于实时目标识别SoC
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649122
Junyoung Park, Byeong-Gyu Nam, H. Yoo
{"title":"A high-throughput 16× super resolution processor for real-time object recognition SoC","authors":"Junyoung Park, Byeong-Gyu Nam, H. Yoo","doi":"10.1109/ESSCIRC.2013.6649122","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649122","url":null,"abstract":"High-resolution image offers more details compared to low-resolution image and consequently improves the accuracy of object recognition. However, higher resolution requires a costly hardware for large image sensor, or computation for additional signal processing. In this paper, we present a high-throughput super resolution processor for high-resolution object recognition. In order to perform super resolution with the real-time object recognition SoC, the algorithm-specific hardware is proposed with 2-D image cache and locality-sensitive hashing accelerator for high-throughput image fetching and searching. As a result, the proposed super resolution processor generates up to 16× higher resolution images with 3,125 fps throughput and 2.0 nJ/pixel energy efficiency, enabling high-resolution pre-processing for real-time object recognition.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121845864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An 8-bit 450-MS/s single-bit/cycle SAR ADC in 65-nm CMOS 基于65nm CMOS的8位450毫秒/秒单位/周期SAR ADC
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649086
Vaibhav Tripathi, B. Murmann
{"title":"An 8-bit 450-MS/s single-bit/cycle SAR ADC in 65-nm CMOS","authors":"Vaibhav Tripathi, B. Murmann","doi":"10.1109/ESSCIRC.2013.6649086","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649086","url":null,"abstract":"A low-energy 8-bit 450-MS/s single-bit/cycle SAR ADC is presented. The design combines top-plate sampling, small unit capacitances (0.75 fF), symmetric DAC switching, and judicious delay optimization around a single high-speed comparator to achieve an ENOB of 7.6 at Nyquist, translating into an FOM of 76 fJ/conversion-step. The converter occupies an active area of 0.035 mm2 in 65-nm CMOS.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127231840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
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