A 0.039mm2 inverter-based 1.82mW 68.6dB-SNDR 10MHz-BW CT-ΣΔ-ADC in 65nm CMOS

Abstract

We propose design techniques for the realization of power- and area-efficient CT-ΣΔ-ADCs in ultra deep submicron CMOS: A resonant single-opamp 3rd order integrator with loss compensation, an inverter-based opamp with digitally-assisted biasing and common mode control, a pseudo-differential modulator topology with quasi-1.5-bit quantization and FIR-DACs with passive DT compensation. A highly compact 41.4 fJ/conv.-step, 77 dB-SFDR, 1.1 V ADC has been implemented to prove these concepts. The entire active analog circuitry in this minimalistic 3rd order modulator consists of only 10 CMOS inverters.