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引用次数: 8
摘要
我们提出了在超深亚微米CMOS中实现功率和面积效率高的CT-ΣΔ-ADCs的设计技术:具有损耗补偿的谐振单opamp三阶积分器，具有数字辅助偏置和共模控制的基于逆变器的opamp，具有准1.5位量化的伪差分调制器拓扑和具有无源DT补偿的fir - dac。一个高度紧凑的41.4 fJ/conv。-step, 77 dB-SFDR, 1.1 V ADC已经实现，以证明这些概念。在这个极简的三阶调制器中，整个有源模拟电路仅由10个CMOS逆变器组成。
A 0.039mm2 inverter-based 1.82mW 68.6dB-SNDR 10MHz-BW CT-ΣΔ-ADC in 65nm CMOS
We propose design techniques for the realization of power- and area-efficient CT-ΣΔ-ADCs in ultra deep submicron CMOS: A resonant single-opamp 3rd order integrator with loss compensation, an inverter-based opamp with digitally-assisted biasing and common mode control, a pseudo-differential modulator topology with quasi-1.5-bit quantization and FIR-DACs with passive DT compensation. A highly compact 41.4 fJ/conv.-step, 77 dB-SFDR, 1.1 V ADC has been implemented to prove these concepts. The entire active analog circuitry in this minimalistic 3rd order modulator consists of only 10 CMOS inverters.
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