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2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)最新文献

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Implementation of the dissection theorem in cadence virtuoso 《节奏大师》中解剖定理的实现
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339438
J. Verbrugghe, B. Moeneclaey, J. Bauwelinck
{"title":"Implementation of the dissection theorem in cadence virtuoso","authors":"J. Verbrugghe, B. Moeneclaey, J. Bauwelinck","doi":"10.1109/SMACD.2012.6339438","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339438","url":null,"abstract":"This paper describes a tool for the Cadence Virtuoso software that implements the Dissection Theorem (DT) or General Network Theorem (GNT) and its applications: the Extra Element Theorem (EET), Chain Theorem (CT) and General Feedback Theorem (GFT). The tool allows a circuit designer to gain additional circuit insight by providing all second- and third-level transfer functions of the DT. In particular, feedback networks are factored into their exact components, enabling a deeper insight into the structure of the loop gain, direct forward transmission and hence closed-loop behaviour.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124123996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis of SRAM cell characteristics based on high-k metal-gate strained Si/Si1−xGex MOSFET with consideration of NBTI/PBTI 考虑NBTI/PBTI的高k金属栅应变Si/Si1−xGex MOSFET SRAM电池特性分析
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339436
B. Ebrahimi, A. Afzali-Kusha
{"title":"Analysis of SRAM cell characteristics based on high-k metal-gate strained Si/Si1−xGex MOSFET with consideration of NBTI/PBTI","authors":"B. Ebrahimi, A. Afzali-Kusha","doi":"10.1109/SMACD.2012.6339436","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339436","url":null,"abstract":"In this paper, we investigate the characteristics of SRAM cells with high-k metal-gate Si/Si1-xGex dual channel structures. The characteristics are compared with those of the unstrained structures. The results show that the strain degrades read SNM slightly while increases read current considerably. In addition, it increases writability while decreases standby power. Moreover, NBTI and PBTI effect for two cases of symmetrical and asymmetrical stresses is investigated. In the symmetrical case, read and write stability don't reduce while read current decreases. For the case of the asymmetrical stress, both read and write stabilities degrade. In addition, read current decreases more than that of the symmetrical case. The results demonstrate while NBTI and PBTI cause less read current reduction in the strained cells, the degradations of other metrics are comparable to those of the unstrained cells.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126580796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
New jerk circuits with mixed-mode oscillations 具有混合模式振荡的新激振电路
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339428
W. Marszalek, Z. Trzaska
{"title":"New jerk circuits with mixed-mode oscillations","authors":"W. Marszalek, Z. Trzaska","doi":"10.1109/SMACD.2012.6339428","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339428","url":null,"abstract":"We propose two jerk circuits that can generate mixed-mode oscillations of various sequences. The circuits' responses comprise both the large (L) and small (s) amplitude oscillations which result in a periodic Ls sequence. The Ls patterns follow the Farey arithmetic when the circuits' parameters bifurcate in certain intervals. One of the two jerk circuits has a Newtonian form as its mathematical model can be derived from the second Newton's law x\" = F/m, with x\" = d2x/dt2 being an “acceleration” variable. Several PSPICE and Matlab simulation results are included.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126293155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A prototype framework for conceptual design of novel analog circuits 新型模拟电路概念设计的原型框架
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339405
C. Ferent, S. Montano, A. Doboli
{"title":"A prototype framework for conceptual design of novel analog circuits","authors":"C. Ferent, S. Montano, A. Doboli","doi":"10.1109/SMACD.2012.6339405","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339405","url":null,"abstract":"This paper presents a reasoning-based synthesis method to design novel analog circuits. In addition to producing circuit topologies and constraints characterizing the topologies, the method finds alternative signal processing flows which represent different conceptual designs that can meet the specification requirements. Each synthesis step aims to remove a design bottleneck by changing the trade-off expressions that link the variables of the trade-off. The main steps of the synthesis method are also illustrated in the paper.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121104790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Performance evaluation of a class E power amplifier loaded by a high-isolation duplexer 采用高隔离双工器负载的E类功率放大器的性能评估
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339450
Ajib Bahi, M. Villegas, A. Diet, G. Baudoin, V. Valenta, J. Tsutsumi
{"title":"Performance evaluation of a class E power amplifier loaded by a high-isolation duplexer","authors":"Ajib Bahi, M. Villegas, A. Diet, G. Baudoin, V. Valenta, J. Tsutsumi","doi":"10.1109/SMACD.2012.6339450","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339450","url":null,"abstract":"This paper presents a performance evaluation of a class-E switched-mode power amplifier, designed in pHEMT GaAs technology, loaded by a high-isolation and low-Insertion Loss (IL) duplexer. This duplexer is based on Surface Acoustic Wave (SAW) technology. Measurements of the duplexer and layout of the class E PA are simulated under Agilent-ADS with a Wideband Code Division Multiple Access signal (WCDMA) in the 1.92 - 1.98 GHz band, for transmission scenario. In this band the amplifier alone achieved 75% to 82% efficiency and 23.5dBm to 24.2dBm output power. The association of the amplifier and the duplexer permitted to reach a drain efficiency of 78% while the output power is 22.7dBm at the central frequency, in the WCDMA band a minimum of 60% efficiency and 21dBm output power is maintained.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"325 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121253754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design considerations on CMOS bulk-driven differential input stages CMOS体驱动差分输入级的设计考虑
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339423
J. M. Carrillo, J. F. Duque-Carrillo, G. Torelli
{"title":"Design considerations on CMOS bulk-driven differential input stages","authors":"J. M. Carrillo, J. F. Duque-Carrillo, G. Torelli","doi":"10.1109/SMACD.2012.6339423","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339423","url":null,"abstract":"Design considerations regarding the DC behaviour of CMOS bulk-driven differential input stages are addressed in this paper. Unlike in conventional gate-driven circuits, the input terminal of a bulk-driven transistor consists of a pn junction, whose real behaviour is critical to determine the input performance of the overall circuit. In this work, the simulated and experimental performance of a bulk-driven differential pair are illustrated and compared in order to draw design hints. The conclusions drawn are applied to the design of a low-voltage bulk-driven voltage-to-current converter in 0.35-μm standard CMOS technology.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128923311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low power and robust 8T/10T subthreshold SRAM cells 低功耗和鲁棒的8T/10T亚阈值SRAM单元
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339437
B. Ebrahimi, H. Afzali-Kusha, A. Afzali-Kusha
{"title":"Low power and robust 8T/10T subthreshold SRAM cells","authors":"B. Ebrahimi, H. Afzali-Kusha, A. Afzali-Kusha","doi":"10.1109/SMACD.2012.6339437","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339437","url":null,"abstract":"In this paper, we propose a novel 8T subthreshold SRAM cell for improving the writing “0” characteristics of the conventional 8T cell. In addition, a new 10T subthreshold SRAM cell based on FinFET structures which has a lower standby power is suggested. The characteristics of the proposed and conventional 8T and 10T structures in 32 nm planar bulk and FinFET technologies are compared. The results show that the 10T structures have better write characteristics thanks to the differential write and consume less static power while the 8T structures have higher read currents. Also, they reveal that FinFET based structures show better read and write characteristics while consuming less static power with less variation in the presence of process variations.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127545109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An efficient linear-time variant simulation technique of oscillator phase sensitivity function 振荡器相位灵敏度函数的高效线性时变模拟技术
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339406
F. Pepe, A. Bonfanti, S. Levantino, P. Maffezzoni, C. Samori, A. Lacaita
{"title":"An efficient linear-time variant simulation technique of oscillator phase sensitivity function","authors":"F. Pepe, A. Bonfanti, S. Levantino, P. Maffezzoni, C. Samori, A. Lacaita","doi":"10.1109/SMACD.2012.6339406","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339406","url":null,"abstract":"This paper presents a fast and accurate simulation technique to evaluate the impulse sensitivity function (ISF) of an oscillator. The proposed method, based on the linear-time variant (LTV) analysis of oscillators, computes the impulse phase response by means of periodic steady-state (PSS) and periodic transfer function (PXF) simulations available in commercial simulators (Spectre, Eldo, etc.). This technique overwhelms the classical simulation method based on transient analysis and injection of charge pulses along the oscillator period in terms of speed, precision and ease of use. The good accuracy of the proposed method has been verified in two oscillator topologies, namely a Van der Pol and a ring oscillator.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128450492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
LDS based tools to ease template construction 基于LDS的工具，简化模板构建
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339417
A. Unutulmaz, G. Dundar, F. Fernandez
{"title":"LDS based tools to ease template construction","authors":"A. Unutulmaz, G. Dundar, F. Fernandez","doi":"10.1109/SMACD.2012.6339417","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339417","url":null,"abstract":"Layout Description Script (LDS) is a domain specific language (DSL) intended to describe analog layouts. This paper introduces an LDS based tool, Capture, and an add-on, LDS Analyzer, for LDS. Capture aims to convert layout images into layout templates. Components of a layout are extracted with this tool and a template is synthesized from the extracted data. LDS Analyzer is an enhanced LDS parser. Analyzer investigates an LDS statement and conducts either simple parsing or enhanced parsing which make use of symbolic variables.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121427652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A CAD framework for the characterization and use of memristor models 一个用于表征和使用忆阻器模型的CAD框架
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) Pub Date : 2012-10-25 DOI: 10.1109/SMACD.2012.6339408
F. García-Redondo, M. López-Vallejo, P. Ituero, C. L. Barrio
{"title":"A CAD framework for the characterization and use of memristor models","authors":"F. García-Redondo, M. López-Vallejo, P. Ituero, C. L. Barrio","doi":"10.1109/SMACD.2012.6339408","DOIUrl":"https://doi.org/10.1109/SMACD.2012.6339408","url":null,"abstract":"In the recent years the missing fourth component, the memristor, was successfully synthesized. However, the mathematical complexity and variety of the models behind this component, in addition to the existence of convergence problems in the simulations, make the design of memristor-based applications long and difficult. In this work we present a memristor model characterization framework which supports the automated generation of subcircuit files. The proposed environment allows the designer to choose and parameterize the memristor model that best suits for a given application. The framework carries out characterizing simulations in order to study the possible non-convergence problems, solving the dependence on the simulation conditions and guaranteeing the functionality and performance of the design. Additionally, the occurrence of undesirable effects related to PVT variations is also taken into account. By performing a Monte Carlo or a corner analysis, the designer is aware of the safety margins which assure the correct device operation.","PeriodicalId":181205,"journal":{"name":"2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130712722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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