{"title":"HardWire LCAs: a risk-free FPGA-to-ASIC migration path","authors":"R. Padovani","doi":"10.1109/WESCON.1995.485290","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485290","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs) combine the density and flexibility of maskprogrammed gate arrays with the convenience and time-to-market benefits of a userprogrammable device. However, the 'overhead' of on-chip programming elements and the circuitry to support them results in FPGA die sizes that are significantly larger than the equivalent-density gate arrays. As a result, FPGA component prices tend to range anywhere from three to ten times the cost of equivalent mask-programmed gate arrays (although this gap is decreasing as IC feature sizes shrink). In high-volume applications with a stable design, FPGA users often consider migrating the design to a gate array as a cost reduction path.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"s1-14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127194790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The evolution of schematic entry: moving from gates to geography","authors":"T. H. Scott","doi":"10.1109/WESCON.1995.485293","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485293","url":null,"abstract":"","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129232319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation challenges for 155 Mbit ATM adapters","authors":"D. Chiswell","doi":"10.1109/WESCON.1995.485420","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485420","url":null,"abstract":"Over the last two years, ATM 155 Mbit adapters for the workstation market have been available for various buses and operating systems. During this time, many lessons have been learned on how to improve an adapter’s performance in workstation and PC server applications as well as decreasing the cost of the adapter. The next year promises to be a big year for ATM with many second generation adapters and switches ready to ship based on the 155Mbit technology.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129269118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automatic hybrid electric Lumina van","authors":"C. Ellers","doi":"10.1109/WESCON.1995.485441","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485441","url":null,"abstract":"A parallel/Series split-drive hybrid system driving a seven passenger Lumina van is described. The series type hybrid uses a heatengine driven generator to charge the batteries and/or supply power to the electric drive motor. Volvo is now showing the Volvo ECC (Environmental Concept Car) which is one of the best examples of the series hybrid concept. MIN. 2 SPEED TRANS. ri FUEL ENGINE","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126492947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault modeling and verification of multi-million transistor VLSI circuits","authors":"D. M. Wu, M. DeBrino, N. Ngo, Jiann-Shiun Yuan","doi":"10.1109/WESCON.1995.485258","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485258","url":null,"abstract":"Ultra-high speed VLSI chips require high-density custom design. This paper describes a tool that extracts fault models/ logic models fkom schematics of multimillion transistor chips. Introduction A VLSI design system provides tools that allow circuit designers to implement their circuit design either at the transistor level or in a hierarchical structure. Through schematic entry, circuit designers perform circuit simulation, optimization, etc. to accomplish their custom design. The size of circuits could range fiom several thousand transistors to several million transistors. The final design presents itself as a layout format. Commercially available VLSI design systems also provide a powem feature to convert this layout to a netlist format. This netlist format,either in SPICE or ASTAP format, is used for simulation and verification of the circuits. ' conventional fault model technique (1) that models each macro manually or semi-manually is no longer applicable to VLSI circuits with multi-million transistors. An automatic approach that directly converts schematics from circuit design database is required to reduce human error, speed up turn around time, and assure the correspondence of logically nets and physically nets. In this paper, an automatic tool, AUTOMOD, that is used to generate fault models for custom designed circuits is described. This tool is also found extremely valuable in capturing design error, such as wrong connection of physically nets, missing pins and wong implementations. It can also be used as a verification tool for physical and logical checking. An initial version of this work was described in a paper by 1","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121589907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using fuzzy logic to derive an optimum embedded application specific architecture","authors":"A. Nguyen, C. Nguyen","doi":"10.1109/WESCON.1995.485452","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485452","url":null,"abstract":"Embedded computer system design is traditionally ad hoc and manual. In most instances, system designers put together a \"straw-man\" system and then evolve from there using classical Queue Network Model (QNM). This approach can cause tunnel vision, since system designers tend to put together a system that is very similar to the predecessor system. The resulting architecture is not derived directly from the set of target application code, instead it is only a modification of the predecessor system. This paper will introduce the concept behind the Architecture Process Flow that uses compiler front-end technique, knowledge base, neural nets and fuzzy logic rules to derive an application specific architecture directly from the target application requirements. A case study on deriving an architecture with limited set of components from the Motorola M68HC11 microcontroller family will be demonstrated using the Architecture Process Flow.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131251492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Motion JPEG and MPEG solutions for multimedia","authors":"D. Fronczak, D. Seltz","doi":"10.1109/WESCON.1995.485493","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485493","url":null,"abstract":"In this paper we present Motion JPEG solutions suitable for consumer non-linear video editing. Following this we show very low cost hardware accelerated MPEG-1 playback implementations. Finally we introduce an optimal multimedia PCI subsystem that includes both technologies. We motivate the discussion by describing recent developments in the industry that are catalysts for explosive growth for these applications in 1996.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133980958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MEMS commercialization activities at MCNC","authors":"K. Markus, M. Walters","doi":"10.1109/WESCON.1995.485297","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485297","url":null,"abstract":"Over the last decade silicon process technology, synonymous with integrated circuit processing, has been increasingly applied to the field of micromechanics, leading to the emerging field of MEMS (microelectromechanical systems). The extensive characterization of silicon processes by the IC industry, integrated with silicon's high Young's modulus and yield-strength, high thermal conductivity and low thermal expansion coefficient makes it one of the best understood and well suited materials available for coupled electronic and mechanical applications.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133823498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}