{"title":"Customer specific microcontrollers","authors":"D. Chakravarty, T. Wong","doi":"10.1109/WESCON.1995.485247","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485247","url":null,"abstract":"ASIC technology trends are driving the emergence of customizable or customerspecific Microcontrollers. These Customizable Microcontrollers integrate the silicon efficiency of Full Custom devices with the flexibility of integrating user definable features of Gate Array and cell based ICS. Through this integration, the customer is able to benefit in a number of ways: * Optimal -with the microcontroller optimized for specific applications with the right combination of features, peripherals and interfaces. * Efficiency -in terms of die Size, power and performance * Integration -allowing miniaturization to take place through device consolidation * Uniqueness -to give competitive advantage to systems designers.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128096886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ISP, JTAG and more for the MAX architecture","authors":"Z.M. Abu-Lebdeh","doi":"10.1109/WESCON.1995.485277","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485277","url":null,"abstract":"6,000 8,000 10.000 12,000 320 400 480 560 168 184 200 216 12 12 12 12 Flexibility, ease of use, and exceptional speed have been the hallmarks of Altera's MAX devices from their inception. A new set of features and functionality is being brought to this successful architecture by two new device families: MAX 9000 and MAX 7000s. In addition to the popular features offered by the existing MAX 7000 devices, the primary enhancements that these two families provide are: In-System Programmability (ISP) and JTAG Boundary-Scan Test capability. MAX 7000s family includes device densities up to 5000 usable gates and are completely pin, function, and programming file compatible with existing MAX 7000 and MAX 7000E devices. MAX 9OOO devices range from 6,000 to 12,000 usable gates and are therefore the highest density Erasable Programmable Logic Devices (EPLDs) offering ISP capability. In addition to ISP and JTAG, MAX 9OOO and MAX 7000s devices include a host of other new features; these will be described in this session as well.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131657042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Partitioning, predictability, P-terms and pinlocking-understanding the new CPLDs","authors":"J. Jenkins","doi":"10.1109/WESCON.1995.485280","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485280","url":null,"abstract":"Bipolar Programmable Logic Arrays were first commercially marketed in the 1970s. They were found to be flexible and had adequate pins, but were also slow and expensive. By eliminating one programmable array, Programmable Array Logic was derived. Both architectures evolved along with customer expectations regarding architectural capabilities. A key architectural direction was that of uniform capability macrocells. This is best demonstrated by the popular 16V8 and 22V10 devices. Both contain flip flops with similar capabilities (setshesets, clock options, feedback, etc.), but the 16V8 has identical product term distribution per macrocell where the 22V10 has a distribution ranging from eight product terms to 16 product terms.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123004571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"New SRAM-based FPGA architectures address new applications","authors":"B. Fawcett","doi":"10.1109/WESCON.1995.485283","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485283","url":null,"abstract":"Since their introduction in 1985, Field Programmable Gate Arrays (FPGAs) have emerged as a leading Application Specific IC (ASIC) technology. By combining the density of gate arrays with the convenience, ease-of-use, and time-to-market benefits of userprogrammable devices, FPGAs have quickly gained the acceptance of system designers worldwide. Recent technology advances continue to expand the range of applications that can be effectively addressed by FPGAs.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"32 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123254225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The advantages of VPSK modulation for data transmission: 10 bits/Hz data compression without loss of signal power","authors":"H. R. Walker","doi":"10.1109/WESCON.1995.485424","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485424","url":null,"abstract":"VPSK modulation is a new and as yet little known modulation method that compresses the RF data transmission bandwidth 104 or 12.61 1 . Unlike other compression methods such as QAM, VPSK does not suffer a loss of S/N wit11 increasing compression. VPSK is BPSK modulation with the data encoded prior to transmission by Single Sideband FM-SC. This results in an Wq value that is theoretically better than that for QPSK, even though the occupied bandwidth is oniy 1/5 as large. Eb/n values of 14 dB for 10-6 BER are being obtained in the field at 10 bits/Hz compression. Due to this low Edq, VPSK is the only high compression method suitable for use on satellites.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120962086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Embedded computing and hardware-software co-design","authors":"W. Wolf, Ti-Yen Yen","doi":"10.1109/WESCON.1995.485423","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485423","url":null,"abstract":"Embedded computers are ubiquitous-microprocesso= are used in simple consumer devices, complex consumer devices such as laser printers and PDAs, telephony, automobiles, and many other applications. The area of CAD which studies the design of the hardware and software components of embedded systems is called hardware-software co-design. Embedded computing systems must fresuently meet hard real-time deadlines as well as soft performance goals. Since embedded system designers control what software will be executed on the hardware platform, they have a great deal of freedom to jointly optimize the hardware and software designs to meet performance and cost goals. Many embedded systems are built with distributed systems, composed of multiple microprocessors, DSPs, and ASICs. This paper surveys the CAD problems posed by embedded computing and recent advances in hardware-software codesign.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115646112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Medical applications of MEMS","authors":"N. Maluf, D. Gee, K. Petersen, G. Kovacs","doi":"10.1109/WESCON.1995.485295","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485295","url":null,"abstract":"Exploiting the materials and processing techniques developed for integrated circuits, silicon micromachining technology has been responsible for fundamental improvements in many, diverse fields of biomedicine. As blood pressure sensors, chemical sensors, micro-chemical reaction and analysis systems, and micro-fluidic control systems, the impact of micromachining on biomedical applications has already been impressive, but is only now poised for dramatic advances. This paper will review current state-of-the-art biomedical applications of micromachining technology such as pressure sensors and biochemical sensors. In addition, we will discuss significant new biomedical innovations on the horizon which make use of micromachining techniques and processes.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127590759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Embedded processor applications for SONET telecommunication systems","authors":"D. Bush","doi":"10.1109/WESCON.1995.485305","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485305","url":null,"abstract":"In order to meet the increased bandwidth requirements of today's telecommunications systems, several designers are using Synchronous Optical NETwork (SONET) protocol to transfer voice and data over fiber optic lines. This solution provides for clear and reliable transport of information between users. At the center of these systems are embedded processors which allow for access to nearly all SONET network information. Additionally, some processors incorporate communications controllers for transfer of SONET Data Communication Channel (DCC) information as well as a UART for data transfers between the host and target systems. Contained on board with the processor are several firmware routines stored in memory that are executed by the processor when instructed by the host system. Performance monitoring, error detection, and alarm conditions are all reported through embedded processor access. This paper gives a brief SONET overview and discusses embedded processor system components, embedded processor functions, firmware development, and design considerations for embedded SONET system applications. Along with describing these areas, a case study of a SONET evaluation system using a Motorola MC68302 embedded processor is provided.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121475239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Recurrent fuzzy logic in speech recognition","authors":"E. Khan","doi":"10.1109/WESCON.1995.485449","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485449","url":null,"abstract":"In this paper, a novel method is presented to combine neural nets with fuzzy logic. The combined technology is based on modified Neufuz (‘71, ‘21, ‘31) using recurrent neural networks. The recurrent information of neural net is directly mapped to a new type of fuzzy logic, called “recurrent” fuzzy logic. Recurrency preserves temporal information and yields superior performance for context dependent applications like handwriting, pattem and speech recognition. It also reduces the convergence time to learn fuzzy logic rules and membership functions. We have used recurrent fuzzy logic approach to solve several problems associated with speech recognition. Simulations show good improvements in accuracx speed of learning and speaker variability for isolated word recognition.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130082204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hardware compatibility issues in the PC card power interface","authors":"T. Hardy","doi":"10.1109/WESCON.1995.485270","DOIUrl":"https://doi.org/10.1109/WESCON.1995.485270","url":null,"abstract":"The PC Card market has moved far beyond its original target of a memory card standard interface. Today there is a constant flow of new applications for PC Card slots. This trend started with fdmodems and went on to GPS, Ethemet, SCSl, pagers, hard disk drives, data acquisition devices, multi-function cards, and wireless everything. As their sophistication increases, so do the power requirements of the new PC Cards. For portable products running on batteries, power management and allocation is of major importance.","PeriodicalId":177121,"journal":{"name":"Proceedings of WESCON'95","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134570318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}